Hardware Description Languages

Hardware description languages (HDLs) are used to describe the architecture and behavior of discrete electronic systems.

HDLs were developed to deal with increasingly complex designs. An analogy is often made to the development of software description languages; from machine code (transistors and solder) to assembly language (netlists) to high-level languages (HDLs).

Top-down, HDL-based system design is most useful in large projects, where several designers or teams of designers are working concurrently. HDLs provide structured development. After major architectural decisions have been made and major components and their connections have been identified, work can proceed independently on subprojects.

Typical Uses for HDLs

HDLs typically support a mixed-level description, where structural or netlist constructs can be mixed with behavioral or algorithmic descriptions. With this mixed-level capability, you can describe system architectures at a high level of abstraction; then incrementally refine a design into a particular component-level or gate-level implementation. Alternatively, you can read an HDL design description into Foundation Express, then direct the compiler to synthesize a gate-level implementation automatically.

Advantages of HDLs

A design methodology that uses HDLs has several fundamental advantages over a traditional gate-level design methodology. Some of the advantages are listed below.

• You can verify design functionality early in the design process and immediately simulate a design written as an HDL description.
  
  Design simulation at this higher level, before implementation at the gate level, allows you to test architectural and design decisions.
  
  
• Foundation Express synthesizes and optimizes logic so you can automatically convert a VHDL description to a gate-level implementation in a given technology.
  
  This methodology eliminates the former gate-level design bottleneck and reduces circuit design time and errors introduced when a VHDL specification is hand-translated to gates. With Foundation Express logic optimization, you can automatically transform a synthesized design to a smaller and faster circuit. You can apply information gained from the synthesized and optimized circuits back to the VHDL description, perhaps to fine-tune architectural decisions.
  
  
• HDL descriptions supply technology independent documentation of a design and its functionality.
  
  Because the initial HDL design description is technology independent, you can later reuse it to generate the design in a different technology, without having to translate from the original technology.
  
  
• An HDL description is more easily read and understood than a netlist or schematic description.
  
  
• VHDL, like most high-level software languages, provides strong type checking.
  
  

A component that expects a four-bit-wide signal type cannot be connected to a three- or five-bit-wide signal; this mismatch causes an error when the HDL description is compiled. If a variable's range is defined as 1 to 15, an error results from assigning it a value of 0. Incorrectly using types is a major source of errors in descriptions. Type checking catches this kind of error in the HDL description even before a design is generated.