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About VHDL

The United States Department of Defense, as part of its Very-High-Speed Integrated Circuit (VHSIC) program, developed VHSIC HDL (VHDL) in 1982. VHDL describes the behavior, function, inputs, and outputs of a digital circuit design. VHDL is similar in style and syntax to modern programming languages but includes many hardware-specific constructs.

VHDL is one of a few HDLs in widespread use today. VHDL is recognized as a standard HDL by the Institute of Electrical and Electronics Engineers (IEEE Standard 1076, ratified in 1987) and by the United States Department of Defense (MIL-STD-454L).

Foundation Express reads and parses the supported VHDL syntax. The “VHDL Constructs” chapter lists all VHDL constructs and includes the level of support provided for each construct.

VHDL divides entities (components, circuits, or systems) into an external or visible part (entity name and connections) and an internal or hidden part (entity algorithm and implementation). After you define the external interface to an entity, other entities can use that entity when they all are being developed. This concept of internal and external views is central to a VHDL view of system design. An entity is defined, relative to other entities, by its connections and behavior. You can explore alternate implementations (architectures) of an entity without changing the rest of the design.

After you define an entity for one design, you can reuse it in other designs as needed. You can develop libraries of entities to use with many designs or a family of designs.

A VHDL hardware model is shown in the following figure.

Figure 1.1 VHDL Hardware Model

A VHDL entity (design) has one or more input, output, or inout ports that are connected (wired) to neighboring systems. An entity is composed of interconnected entities, processes, and components, all which operate concurrently. Each entity is defined by a particular architecture, which is composed of VHDL constructs such as arithmetic, signal assignment, or component instantiation statements.

In VHDL, independent processes model sequential (clocked) circuits, using flip-flops and latches, and combinatorial (unclocked) circuits, using only logic gates. Processes can define and call (instantiate) subprograms (subdesigns). Processes communicate with each other by signals (wires).

A signal has a source (driver), one or more destinations (receivers), and a user-defined type, such as “color” or “number between 0 and 15.”

VHDL provides a broad set of constructs. With VHDL, you can describe discrete electronic systems of varying complexity (systems, boards, chips, or modules) with varying levels of abstraction.

VHDL language constructs are divided into three categories by their level of abstraction: behavioral, dataflow, and structural. These categories are described below.

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