Design Hierarchy

Foundation Express maintains the hierarchical boundaries you define when using the structural view in VHDL. These boundaries have two major effects.

• Each design entity specified in your VHDL description is synthesized separately and is maintained as a distinct design. The constraints for the design are maintained, and each design entity can be optimized separately in Foundation Express.
  
  
• Component instantiations within VHDL descriptions are maintained during input. The instance name you give each user-defined entity is carried through to the gate-level implementation.
  
  

The chapter “Describing Designs” discusses design entities, and the “Concurrent Statements” chapter discusses component instantiations.

NOTE

Foundation Express does not automatically maintain or create a hierarchy of other nonstructural VHDL constructs such as blocks, processes, loops, functions, and procedures. These elements of a VHDL description are translated in the context of their design. After reading in a VHDL design, you can group together the logic of a process, function, or procedure within the Foundation Express Implementation graphical user interface (GUI).

The choice of hierarchical boundaries has a significant effect on the quality of the synthesized design. Using Foundation Express, you can optimize a design while preserving these hierarchical boundaries. However, Foundation Express only partially optimizes logic across hierarchical modules. Full optimization is possible across those parts of the design hierarchy that are collapsed in Foundation Express.