In VHDL, you must assign a data type to all ports, signals, and variables. The data type of an object defines the operations that can be applied to the object. For example, the AND operator is defined for objects of type BIT but not for objects of type INTEGER.
Data types are also important when your design is synthesized. The data type of an object determines its size (bit width) and its bit organization. The proper choice of data types greatly improves design quality and helps minimize errors.
See the “Data Types” chapter for a discussion of VHDL data types.
