VHDL is a strongly typed language. Every constant, signal, variable, function, and parameter is declared with a type, such as BOOLEAN or INTEGER, and can hold or return only a value of that type.
VHDL predefines abstract data types, such as BOOLEAN, which are part of most programming languages, and hardware-related types, such as BIT, found in most hardware languages. Predefined VHDL types are declared in the STANDARD package, which is supplied with all VHDL implementations.
This chapter describes VHDL data types and their uses. Data type information is included in the following sections.