The advantage of strong typing is that VHDL tools can catch many common design errors, such as assigning an eight-bit value to a four-bit-wide signal or incrementing an array index out of its range.
The following example code shows the definition of a new type, BYTE, as an array of eight bits, and a variable declaration, ADDEND, that uses this type.
type BYTE is array(7 downto 0) of BIT;
variable ADDEND: BYTE;The predefined VHDL data types are built from the basic VHDL data types. Some VHDL types are not supported for synthesis, such as REAL and FILE.
The examples in this chapter show type definitions and associated object declarations. Although each constant, signal, variable, function, and parameter is declared with a type, only variable and signal declarations are shown in this chapter's examples. Constant, function, and parameter declarations are shown in the “Describing Designs” chapter.
VHDL also defines subtypes, which are defined as subsets of other types. Anywhere a type definition can appear, a subtype definition can also appear. The difference between a type and a subtype is that a subtype is a subset of a previously defined parent (or base) type or subtype. Overlapping subtypes of a given base type can be compared against and assigned to each other. All integer types, for example, are technically subtypes of the built-in integer base type (see the “Array Attributes” section of this chapter). Subtypes are further described later in this chapter.
