Overview

In the following VHDL fragment, A and B are operands, + is an operator, and A + B is an expression.

C := A + B; -- Computes the sum of two values

You can use expressions in many places in a design description. Expressions can be used in any of the following ways.

• Assigned to variables or signals or used as the initial values of constants
  
  
• Used as operands to other operators
  
  
• Used for the return value of functions
  
  
• Used for the IN parameters in a subprogram call
  
  
• Assigned to the OUT parameters in a procedure body
  
  
• Used to control the actions of statements like if, loop, and case
  
  

To understand expressions for VHDL, consider the individual components of operators and operands.

Operators

• Logical operators
  
  
• Relational operators
  
  
• Adding operators
  
  
• Unary (sign) operators
  
  
• Multiplying operators
  
  
• Miscellaneous arithmetic operators
  
  

Operands

• Computable operands
  
  
• Literals
  
  
• Identifiers
  
  
• Indexed names
  
  
• Slice names
  
  
• Aggregates
  
  
• Attributes
  
  
• Function calls
  
  
• Qualified expressions
  
  
• Type conversions