A VHDL operator is characterized by the following.
You can define new operators, like functions, for any type of operand and result value. The predefined VHDL operators are listed in the table below.
| Type | Operators | Precedence | |||||
|---|---|---|---|---|---|---|---|
| Logical | and | or | nand | nor | xor | Lowest | |
| Relational | = | /= | < | <= | > | >= | |
| Adding | + | - | & | ||||
| Unary (sign) | + | - | |||||
| Multiplying | * | / | mod | rem | |||
| Miscellaneous | ** | abs | not | Highest |
Each row in the table lists operators with the same precedence. Each row's operators have greater precedence than those in the row above. An operator's precedence determines whether it is applied before or after adjoining operators.
The following example shows several expressions and their interpretations.
A + B * C = A + (B * C)
not BOOL and (NUM = 4) = (not BOOL) and (NUM = 4)VHDL allows existing operators to be overloaded (applied to new types of operands). For example, the AND operator can be overloaded to work with a new logic type. For more information, see the “Operator Overloading” section of the “Describing Designs” chapter.
Operands of a logical operator must be of the same type. The logical operators AND, OR, NAND, NOR, XOR, and NOT accept operands of type BIT, type BOOLEAN, and one-dimensional arrays of BIT or BOOLEAN. Array operands must be the same size. A logical operator applied to two array operands is applied to pairs of the two arrays' elements.
The following example shows logical signal declarations and their logical operations.
signal A, B, C: BIT_VECTOR(3 downto 0);
signal D, E, F, G: BIT_VECTOR(1 downto 0);
signal H, I, J, K: BIT;
signal L, M, N, O, P: BOOLEAN;
A <= B and C;
D <= E or F or G;
H <= (I nand J) nand K;
L <= (M xor N) and (O xor P); Normally, to use more than two operands in an expression, you must use parentheses to group the operands. Alternatively, you can combine a sequence of AND, OR, or XOR operators without parentheses, such as the following sequence.
A and B and C and D
However, sequences with different operators do require parentheses, as shown in the following example.
(A or B) xor C
The next example uses the declarations from the logical operators example to show some common errors. The resulting synthesized circuit follows this example.
H <= I and J or K; -- Parenthesis required;
L <= M nand N nand O nand P; -- Parenthesis required;
A <= B and E; -- Operands must be the same size;
H <= I or L; -- Operands must be the same type;Figure 5.1 Circuit for Common Errors Using Logical Operators |  |
Relational operators, such as = or >, compare two operands of the same base type and return a BOOLEAN value.
IEEE VHDL defines the equality (=) and inequality (/=) operators for all types. Two operands are equal if they represent the same value. For array and record types, IEEE VHDL compares corresponding elements of the operands.
IEEE VHDL defines the ordering operators (<, <=, >, and >=) for all enumerated types, integer types, and one-dimensional arrays of enumeration or integer types.
The internal order of a type's values determines the result of the ordering operators. Integer values are ordered from negative infinity to positive infinity. Enumerated values are in the same order as they were declared, unless you have changed the encoding.
If you set the encoding of your enumerated types (see the “Enumeration Encoding” section of the “Data Types” chapter), the ordering operators compare your encoded value ordering, not the declaration ordering. Because this interpretation is specific to Foundation Express, a VHDL simulator continues to use the declaration's order of enumerated types.
The relative order of two array values is determined by comparing each pair of elements in turn, beginning from the left bound of each array's index range. If a pair of array elements is not equal, the order of the different elements determines the order of the arrays. For example, bit vector 101011 is less than 1011 because the fourth bit of each vector is different, and 0 is less than 1.
If the two arrays have different lengths, and the shorter array matches the first part of the longer array, the shorter one is ordered before the longer. Thus, the bit vector 101 is less than 101000. Arrays are compared from left to right, regardless of their index ranges (to or downto).
The following example shows several expressions that evaluate to TRUE.
'1' = '1'
"101" = "101"
"1" > "011" -- Array comparison
"101" < "110"To interpret bit vectors such as 011 as signed or unsigned binary numbers, use the relational operators defined in the Foundation Express std_logic_arith package. The third line in the above example evaluates to FALSE if the operands are of type UNSIGNED.
UNSIGNED'"1" < UNSIGNED'"011" -- Numeric comparison
The following example shows some relational expressions. The resulting synthesized circuit follows the example.
signal A, B: BIT_VECTOR(3 downto 0);
signal C, D: BIT_VECTOR(1 downto 0);
signal E, F, G, H, I, J: BOOLEAN;
G <= (A = B);
H <= (C < D);
I <= (C >= D);
J <= (E > F); Figure 5.2 Circuit for Relational Operators | |
Adding operators include arithmetic and concatenation operators.
The arithmetic operators + and - are predefined by Foundation Express for all integer operands. These addition and subtraction operators perform conventional arithmetic, as shown in the example below. For adders and subtracters more than four bits wide, a synthetic library component is used. (See the “Foundation Express Compiler Directives” chapter.)
The concatenation (&) operator is predefined for all one-dimensional array operands. The concatenation operator builds arrays by combining the operands. Each operand of & can be an array or an element of an array. Use & to add a single element to the beginning or end of an array, to combine two arrays, or to build an array from elements, as shown in the example below. The schematic for the resulting circuits follow the example.
signal A, D: BIT_VECTOR(3 downto 0);
signal B, C, G: BIT_VECTOR(1 downto 0);
signal E: BIT_VECTOR(2 downto 0);
signal F, H, I: BIT;
signal J, K, L: INTEGER range 0 to 3;
A <= not B & not C; -- Array & array
D <= not E & not F; -- Array & element
G <= not H & not I; -- Element & element
J <= K + L; -- Simple addition Figure 5.3 Circuits for Adding Operators | |
A unary operator has only one operand. Foundation Express predefines unary operators + and - for all integer types. The + operator has no effect. The - operator negates its operand as shown in the following example.
5 = +5
5 = -(-5)The example below shows how unary negation is synthesized. The resulting circuit follows the example.
signal A, B: INTEGER range -8 to 7;
A <= -B;Figure 5.4 Circuit for Unary (Signed) Operators | |
Foundation Express predefines the multiplying operators (*, /, mod, and rem) for all integer types.
Foundation Express places some restrictions on the supported values for the right operands of the multiplying operators, as follows.
The example below shows some uses of the multiplying operators whose right operands are all powers of 2. The resulting synthesized circuit follows the example.
signal A, B, C, D, E, F, G, H: INTEGER range 0 to 15;
A <= B * 4;
C <= D / 4;
E <= F mod 4;
G <= H rem 4;Figure 5.5 Circuit for Multiplying Operators with Powers of 2 | |
The example below shows two multiplication operations, one with a four-bit operand times a two-bit constant (B * 3) and one with two five-bit operands (X * Y). Because the synthetic library is enabled by default, these multiplication operations are implemented as synthetic library cells. A figure of the resulting circuit follows the example.
signal A, B: INTEGER range 0 to 15;
signal Y, Z: INTEGER range 0 to 31;
signal X: INTEGER range 0 to 1023;
. . .
A <= B * 3;
X <= Y * Z; Figure 5.6 Circuit for Multiply Operator (*) Using Synthetic Cells | |
Foundation Express predefines the absolute value (abs) and exponentiation (**) operators for all integer types. One Foundation Express restriction placed on ** follows.
Exponentiation: left operand must have a computable value of 2. (See the “Computable Operands” section of this chapter.)
The example below shows how these operators are used and synthesized. The figure for the resulting circuit follows the example.
signal A, B: INTEGER range -8 to 7;
signal C: INTEGER range 0 to 15;
signal D: INTEGER range 0 to 3;
A <= abs(B);
C <= 2 ** D;Figure 5.7 Circuit for Miscellaneous Arithmetic Operators | |
