A concurrent signal assignment is equivalent to a process containing that sequential assignment. Thus, each concurrent signal assignment defines a new driver for the assigned signal. The simplest form of the concurrent signal assignment follows.
target <= expression;
Target is a signal that receives the value of expression.
The example below shows the value of the expression A and B concurrently assigned to signal Z.
BLK: block
signal A, B, Z: BIT;
begin
Z <= A and B;
end block BLK;The other two forms of concurrent signal assignment are conditional signal assignment and selected signal assignment.
Another form of concurrent signal assignment is the conditional signal assignment. The syntax follows.
target <= { expression when condition else }
expression;Target is a signal that receives the value of an expression. The expression used is the first one whose Boolean condition is TRUE.
When a conditional signal assignment statement is executed, each condition is tested in order, as written. The first condition that evaluates TRUE has its expression assigned to target. If no condition is TRUE, the final expression is assigned to the target. If two or more conditions are TRUE, only the first one is effective, just like the first TRUE branch of an if statement.
The following example shows a conditional signal assignment, where the target is the signal Z. Signal Z is assigned from one of the signals A, B, or C. The signal depends on the value of the expressions ASSIGN_A and ASSIGN_B. Note that the assignment of A takes precedence over that of B, and the assignment of B takes precedence over that of C, because the first TRUE condition controls the assignment. The resulting circuit is shown in the figure following the example.
Z <= A when ASSIGN_A = '1' else
B when ASSIGN_B = '1' else
C;Figure 7.6 Circuit for Conditional Signal Assignment |  |
The following example shows a process equivalent to the example of the conditional signal assignment.
process(A, ASSIGN_A, B, ASSIGN_B, C)
begin
if ASSIGN_A = '1' then
Z <= A;
elsif ASSIGN_B = '1' then
Z <= B;
else
Z <= C;
end if;
end process;The final kind of concurrent signal assignment is the selected signal assignment. The syntax follows.
with choice_expression select
target <= { expression when choices, }
expression when choices;Target is a signal that receives the value of an expression. The expression selected is the first one whose choices include the value of choice_expression. The syntax of choices is the same as that of the case statement.
choice { | choice }Each choice can be either a static expression (such as 3) or a static range (such as 1 to 3). The type of choice_expression determines the type of each choice. Each value in the range of the choice_expression type must be covered by one choice.
The final choice can be others, which matches all remaining (unchosen) values in the range of the choice_expression type. The others choice, if present, matches choice_expression only if none of the other choices match.
The with...select statement evaluates choice_expression and compares that value to each choice value. The when clause with the matching choice value has its expression assigned to target.
The following restrictions are placed on choices.
The following example shows target Z assigned from A, B, C, or D. The assignment depends on the current value of CONTROL. The resulting circuit is shown in the figure following the example.
signal A, B, C, D, Z: BIT;
signal CONTROL: bit_vector(1 down to 0);
. . .
with CONTROL select
Z <= A when "00",
B when "01",
C when "10",
D when "11";Figure 7.7 Circuit for Selected Signal Assignment | |
The following example shows a process equivalent to the previous example of selected signal assignment.
process(CONTROL, A, B, C, D)
begin
case CONTROL is
when 0 =>
Z <= A;
when 1 =>
Z <= B;
when 2 =>
Z <= C;
when 3 =>
Z <= D;
end case;
end process;