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Component Instantiations

A component instantiation references a previously defined hardware component, in the current design, at the current level of hierarchy. You can use component instantiations to define a design hierarchy. You can also use parts not defined in VHDL, such as components from an FPGA technology library, parts defined in the Verilog hardware description language, or the generic technology library. Component instantiation statements can be used to build netlists in VHDL.

A component instantiation statement indicates the following.

The syntax follows.

   instance_name : component_name port map (
                   [ port_name => ] expression
                   {, [ port_name => ] expression } );

instance_name names this instance of the component type component_name.

The port map connects each port of this instance of component_name to a signal-valued expression in the current entity. The value of expression can be a signal name, an indexed name, a slice name, or an aggregate. If expression is the VHDL reserved word open, the corresponding port is left unconnected.

You can map ports to signals by named or positional notation. You can include both named and positional connections in the port map, but you must place all positional connections before any named connections.

NOTE

For named association, the component port names must exactly match the declared component's port names. For positional association, the actual port expressions must be in the same order as the declared component's port order.

The example below shows a component declaration (a 2-input NAND gate) followed by three equivalent component instantiation statements.

    component ND2    
       port(A, B: in BIT; C: out BIT);    
    end component;    
    . . .    
    signal X, Y, Z:  BIT;    
    . . .    
    U1: ND2 port map(X, Y, Z);               -- positional    
    U2: ND2 port map(A => X, C => Z, B => Y);-- named    
    U3: ND2 port map(X, Y, C => Z);          -- mixed

The following example shows the component instantiation statement defining a simple netlist. The three instances, U1, U2, and U3 are instantiations of the 2-input NAND gate component declared in the example of component declaration and instantiations. The resulting circuit is shown in the figure following the example.

   signal TEMP_1, TEMP2: BIT;    
    . . .    
      U1: ND2 port map(A, B, TEMP_1);    
      U2: ND2 port map(C, D, TEMP_2);    
      U3: ND2 port map(TEMP_1, TEMP_2, Z);

Figure 7.8 Circuit for Simple Netlist

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