Three-State Inference

Foundation Express can infer three-state gates (high-impedance output) from enumeration encoding in VHDL. After inferring the gates, Foundation Express maps the gates to a specified technology library. See the “Enumeration Encoding” section of the “Data Types” chapter for more information.

When a variable is assigned the value of Z, the output of the three-state gate is disabled.

The following example shows how to create a three-state gate in VHDL.

    signal OUT_VAL, IN_VAL: std_logic;     
    ...     
    if (COND) then     
        OUT_VAL <= IN_VAL;     
    else     
        OUT_VAL <= 'Z';     -- assigns high-impedance     
    end if;

You can assign a high impedance value to a four-bit wide bus with ZZZZ.

One three-state device is inferred from a single process. The following example shows how to infer one three-state device from a single process.

   process (sela, a, selb, b) begin     
     t <= 'z';     
        if (sela = '1') then     
          t <= a;     
        if (selb = '1') then     
          t <= b;     
   end process;

The example below shows how to infer two three-state devices.

   process (sela, a) begin     
       if (sela = `1') then     
        t = a;     
       else t = `z';     
   end process;

   process (selb, b) begin     
       if (selb = `1') then     
         t = b;     
       else t = `z';     
    end process;

The VHDL conditional assignment can also be used to infer three-state devices.

Assigning the Value Z

Assigning the value Z to variables is allowed. The value Z can also appear in function calls, return statements, and aggregates. However, except for comparisons to Z, you cannot use Z in an expression.

The example below shows the incorrect use of the value Z in an expression.

    OUT_VAL <= 'Z' and IN_VAL;     
    ...

The following example shows the correct expression comparing to Z.

    if IN_VAL = 'Z' then     
    ...

WARNING

Expressions comparing to Z are synthesized as though values are not equal to Z.

For example, the following expression

    if X = 'Z' then     
    ...

is synthesized as

    if FALSE then     
    ...

If you use expressions comparing values to Z, the presynthesis and post-synthesis simulation results might differ. For this reason, Foundation Express issues a warning when it synthesizes such comparisons.

Latched Three-State Variables

When a variable is latched (or registered) in the same process in which it is three-stated, the enable of the three-state Z is also latched (or registered). This process is shown in the example below. The resulting circuit follows the example.

   -- Creates a flip-flop on input and on enable     
   if (THREESTATE = '0') then     
       OUTPUT <= 'Z';     
   elsif (rising_edge) then     
       if (CONDITION) then     
           OUTPUT <= INPUT;     
       end if;     
   end if;

Figure 8.21 Circuit for a Three-State Inferred with Registered Enable

In the example of the three-state inferred with registered enable, the three-state gate has a registered enable signal. The following example uses two processes to instantiate a three-state with a flip-flop only on the input. The resulting circuit follows the example.

   entity LATCH_3S is     
     port(CLK, THREESTATE, INPUT: in std_logic;     
          OUTPUT: out std_logic; CONDITION: in Boolean);     
   end LATCH_3S;

   architecture EXAMPLE of LATCH_3S is     
     signal TEMP: std_logic;     
   begin

     process(CLK, CONDITION, INPUT)     
     begin      -- creates three-state     
       if (rising_edge) then     
         if (CONDITION) then     
             TEMP <= INPUT;     
         end if;     
       end if;     
     end process;     
     process(THREESTATE, TEMP)     
     begin     
       if (THREESTATE = '0') then     
           OUTPUT <= 'Z';     
       else     
           OUTPUT <= TEMP;     
       end if;     
     end process;     
   end EXAMPLE;