LAYOUT: CCLK
CCLK is the download clock.
Many boards contain two or more FPGAs in a daisy chain configuration. The Cclk is taken from one FPGA to the other.
CCLK has a very fast slew rate driver and that is can cause a lot of reflections on the clock line.
Inside the FPGA the CCLK is first routed to the CCLK pin and then taken back inside to the configuration circuit.
- Treat the Cclk line as a transmission line. Terminate it properly.
Ideas : active termination via two Shottky diodes, or a slow slew rate driver mounted immediately after the first device.