PPT 슬라이드

Design Synthesis & Retargetability

Synergy HDL

Synthesis

Cadence/Synergy

Synthesis

Libraries

Design Optimization

for FPGAs

FPGA Designer

Post Implementation

Netlist & SDF

PLD & FPGA Designer

Schematic Redraw

Functional Simulation / Verification

OpenSIM BackPlane

Netlist Creation

VerilogLink/VHDLLink

Timing

Simulation

Verilog-XL,

LeapFROG

or

Rapidsim

Simulation

Libraries

*XNF

*Xilinx Netlist Format

Simulation

Libraries

VHDL, VERILOG

Timing Backannotation

X-BLOX

Design Flow

이전 슬라이드

다음 슬라이드

첫 슬라이드로 이동

그래픽 버전 보기