PPT ½½¶óÀ̵å
Design Entry
Concept
Mixed-Level
Schematic/HDL
Netlist
Information
Design Synthesis & Retargetability
Synergy HDL/VHDL
Synthesis
Synthesis
Libraries
Design Optimization/ Partitionning for PLDs
PLD Designer
Design Optimization
for FPGAs
FPGA Designer
Post Implementation
Netlist & SDF
PLD & FPGA Designer
Schematic Redraw
Functional Simulation
Verilog XL,
Leapfrog
Functional Simulation / Verification
OpenSIM BackPlane
Netlist Creation
VerilogLink/VHDLLink
Timing
Simulation
Verilog-XL,
Leapfrog
Simulation
Libraries
Timing Backannotation
*EDIF, XNF
Verilog, VHDL
**SDF, *EDIF
*Standard Interface Netlist Format
** Standard Delay Format
Simulation
Libraries
VHDL, VERILOG
Design Flow
M1
ÀÌÀü ½½¶óÀ̵å
´ÙÀ½ ½½¶óÀ̵å
ù ½½¶óÀ̵å·Î À̵¿
±×·¡ÇÈ ¹öÀü º¸±â