Multi-Source IntegrationMixed-Level Flows

Check Point Verification

EDIF

VHDL

Verilog

SDF

Knowledge

Driven Implementation

Design Source Integration

HDL

Schematic

Existing Designs

Cores

StandardsBased

• Enables multiple sources and multiple EDA vendors in the same flow

• Allows team development

• Reduces design source translations

• Design the way you are used to

• Enables rapid, accurate iterations

• Works well within existing ASIC flows

• Facilitates Design Reuse

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