Clock Doubling and Mirroring

• Clock mirror with less than 100 ps skew

  • simplifies PCB clock distribution

Virtex

Zero-Delay Internal Clock Buffer

37 MHz

74 MHz #1

74 MHz #2

74 MHz Internal

37 MHz Internal

System Clock

SDRAM

Inside FPGA

Inside FPGA

SystemClock

1 Input Load

Exactly

Aligned

Actual HDTV

Customer Example

SDRAM

DLL 2

DLL 1

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