Input Arrival Calculation
Inputs are constrained by their input arrival.
Example: When does data arrive at pin D1?
- After the clock trigger, data delay is TCKO + Tnet + Tpad + TC1
- Delay C1 net delays, or other combinatorial elements on the board
- Delay TCD is the delay through the FPGA clock distribution network
Tarrival = Tcko + Tnet + Tpad + TC1 - TCD