Xilinx CPLD ChipViewer

WebPACK ChipViewer Version 2.1WP2.1

WebPACK is a free, downloadable, modular design entry and implementation system for developing Xilinx CPLD designs on PCs.

The ChipViewer module is used to view the fitter placement of design netlists in Xilinx CPLD devices and to specify pin locations prior to fitter placement. The ChipViewer is an add-on and can only be used if installed with the CPLD_Fitter Module.

The ChipViewer is compatible with the following other WebPACK module:

• CPLD_Fitter Version 2.1WP2.x:
  The XC9500-series CPLD fitter can be used to implement designs from either of two sources:
  • Design netlists prepared using any of the supported third-party Xilinx Alliance EDA vendors, under control of the included Xilinx Design Manger user interface.
  • VHDL, Verilog HDL or ABEL language designs prepared using the WebPACK HDL_ABEL module.

The ChipViewer module consists of the following application programs:

• ChipViewer, Version 2.1i_sp1.

To review the known issues for this module, refer to the ChipViewer Release Notes.

To view the revision history for this module, refer to the ChipViewer Revision History for KOREAN.
 

Copyright Ó 1999 Xilinx, Inc.  All rights reserved.

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