XC9500 Device Fitter Tools

WebPACK CPLD_Fitter Version 2.1WP2.1

WebPACK is a free, downloadable, modular design entry and implementation system for developing Xilinx CPLD designs on PCs.

The CPLD_Fitter module is used to implement (fit) design netlists into a Xilinx XC9500-series CPLD device. The CPLD fitter can be used to implement designs from either of two sources:

• Design netlists prepared using any of the supported third-party Xilinx Alliance EDA vendors, under control of the included Xilinx Design Manger user interface.
   
• VHDL, Verilog HDL or ABEL language designs prepared using the WebPACK HDL_ABEL module.
   

The CPLD_Fitter module is compatible and can be use with any of the following other WebPACK modules:

• HDL_ABEL Version 2.1WP2.x:
  VHDL, Verilog and ABEL compiler and design environment, including Project Navigator user interface for seamless, front-to-back design development.
   
• Programmer Version 2.1WP2.x:
  JTAG download software for programming Xilinx XC9500-series CPLDs.
   
• ChipViewer Version 2.1WP2.x:
  The ChipViewer module used to view the fitter placement of design netlists in Xilinx CPLD devices and to specify pin locations prior to fitter placement.

  Note: Differences in the last field of the version string ("x" above) do not impact compatibility between WebPACK modules.

The CPLD_Fitter module consists of the following application programs:

• CPLD fitter, Version 2.1i_sp1.
• Xilinx Design Manger graphical user interface, Version 2.1i_sp1.
• Timing Analyzer, Version 2.1i_sp1.
• Constraints Editor, Version 2.1i_sp1.
• LogiBLOX, Version 2.1i_sp1.

  The CPLD_Fitter module also contains VHDL and Verilog Simprims libraries required to perform timing simulation using a 3rd-party HDL simulator.

  Note: The CPLD_Fitter module does not contain Dynatext document viewer, design capture libraries or synthesis libraries.

If the CPLD_Fitter module is installed on the same system as a CD-based Xilinx software product (Alliance or Foundation), you may need to manually update your system environment to switch between these two tools. Please refer to the detailed instructions.

To review the known issues for this module, refer to the CPLD_Fitter Release Notes.

To view the revision history for this module, refer to the CPLD_Fitter Revision History for KOREAN.
 

Copyright Ó 1999 Xilinx, Inc.  All rights reserved.

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