Output File Format

This option allows you to indicate that you want the software to create a timing simulation output file for use with an external simulator. You can select EDIF, Verilog, or VHDL output file formats. The output file name will be time_sim. You can also select None to produce no Simulation file. By default, this option is set to None.

If you choose to simulate using either VHDL or Verilog file formats, you will need to use the simulation libraries provided with WebPACK. If Xilinx_CPLD is the directory in which WebPACK was installed then the VHDL simulation libraries are located in the Xilinx_CPLD\VHDL\src\simprims directory and the Verilog library files are located in the Xilinx_CPLD\Verilog\src\simprims directory. Refer to the documentation provided with your simulator for information on how to use these libraries.

Note: When simulating in Verilog format it is necessary to include the glbl.v file provided in the Xilinx_CPLD/Verilog/src directory as a source file in the simulator. See here for more information.