Index

?:= - Assignment Operator

?= - Assignment Operator

@Setsize - Set Indexing
@Ifb - If Blank Directive
@Ifdef - If Defined Directive
@Ifiden - If Identical Directive
@Ifnb - If Not Blank Directive
@Ifndef - If Not Defined Directive
Directives
@Alternate - Alternate Operator Set
@Standard - Standard Operators Directive
@Ifniden - If Not Identical Directive
@Const - Constant Declarations
@Include - Include Directive
@Exit - Exit Directive
@Irp - Indefinite Repeat Directive
@If - If Directive
@Irpc - Indefinite Repeat, Character Directive
@Carry - Maximum Bit-width for Arithmetic Functions
@Repeat - Repeat Directive
@Message - Message Directive
@Expr - Expression Directive
@Onset
@Dcset - Don't Care Set
@Page - Page Directive
@Radix - Default Base Numbering Directive

@DCState

@directive

= Constant Declarations

= - Assignment Operator

Supported ABEL Dot Extensions

4-Bit Comparator

4-Bit Universal Counter

A

ABEL

ABEL Design Examples

ABEL Design Flow

ABEL-HDL

Building a Lower-level ABEL-HDL Source
Building a Top-level ABEL-HDL Source

ABEL-HDL Design Considerations

ABEL-HDL language

Functional_block Keyword
Interface Keyword (lower-level)
Interface - Declare Modules for Hierarchical Designs
ABEL Syntax Reference
Interface Keyword (top-level)

ABEL-HDL Reference

ABEL-HDL Sources

Device-independent ABEL-HDL Sources

adders

@Carry - Maximum Bit-width for Arithmetic Functions

addition

AND

Arguments and Argument Substitution

Application Error -- Call to Undefined Dynalink

Arguments

arithmetic functions

@Carry - Maximum Bit-width for Arithmetic Functions

Arithmetic Functions - Component Selection Guide

arithmetic operators

Assigning Global Nets in Design Manager

Assigning Global Nets in Project Navigator

Assigning Global Nets Manually in ABEL

Assigning Pins in ABEL

Assigning Pins Manually

assignment operators

Async_reset and Sync_reset

Async_reset

attributes

Istype 'com' - Combinational Signal Attribute
Istype 'keep' - Do Not Collapse Signal
Istype 'neg' - Unspecified Logic is 1
Istype 'pos' - Unspecified Logic is 0
Istype 'xor' - XOR Gate in Target Device
Istype 'buffer' - Non-inverter attribute
Istype 'collapse' - Collapse Combinational Node Attribute
Istype 'dc' - Unspecified Logic is Don't Care
Istype 'invert' - Inverter Attribute
Istype 'reg' - Clocked Memory Element
Istype 'reg_D' - D Flip-flop Clocked
Istype 'reg_G' - D Flip-flop Gated Clock Memory Element
Istype 'reg_JK' - JK Flip-flop Clocked Memory Element
Istype 'reg_SR' - SR Flip-flop Clocked Memory Element
Istype 'reg_T' - T Flip-flop Clocked Memory Element
Istype 'retain' - Do Not Minimize This Output

B

base numbering

@Radix - Default Base Numbering Directive

Basic Syntax

Blacjack Machine Description

black box designs

Pin-to-pin vs. Detailed Descriptions for Registered Designs

Blackjack Machine - BINBCD

Blackjack Machine - BJACK

Blackjack Machine - MUXADD PLD

Blackjack Machine Implementation

Blackjack Machine Operation

Blocks

Equation Blocks

buffer

Invert/Buffer Example
Istype 'invert' and 'buffer'

Buffers and Inverters - Component Selection Guide

C

carry logic

@Carry - Maximum Bit-width for Arithmetic Functions

Case keyword

Case Keyword

Choosing Identifiers

Clocked Memory Element

Istype 'reg_JK' - JK Flip-flop Clocked Memory Element
Istype 'reg_G' - D Flip-flop Gated Clock Memory Element
Istype 'reg_SR' - SR Flip-flop Clocked Memory Element
Istype 'reg_D' - D Flip-flop Clocked
Istype 'reg_T' - T Flip-flop Clocked Memory Element
Istype 'reg' - Clocked Memory Element

collapse

Istype 'keep' - Do Not Collapse Signal
Istype 'collapse' - Collapse Combinational Node Attribute

combinational nodes

Istype 'collapse' - Collapse Combinational Node Attribute

Combinational Signal

Istype 'com' - Combinational Signal Attribute

Combined Logic Descriptions

Comments

comparator

4-Bit Comparator

comparators

@Carry - Maximum Bit-width for Arithmetic Functions

Comparators - Component Selection Guide

Constant Declarations

@Const - Constant Declarations

Constants

Constants
= Constant Declarations
Special Constants

Controlling Initial States in ABEL

Controlling Logic Optimization

Controlling Power Consumption

Controlling Power Consumption in ABEL

Controlling Register Initial States

Controlling Slew Rate

counter

4-Bit Universal Counter

counters

@Carry - Maximum Bit-width for Arithmetic Functions

Counters - Component Selection Guide

CPLD Application Notes

CPLD Attributes

CPLD Attributes Used in a User Constraints File (UCF)

CPLD Attributes Used in ABEL Files

CPLD Attributes Used in Schematics

CPLD Design Techniques

Creating Bidirectional Signals

Creating Counters

Creating Latches

Creating Read-Back Registers

D

D Flip-flop

Istype 'reg_G' - D Flip-flop Gated Clock Memory Element
Istype 'reg_D' - D Flip-flop Clocked

declarations

= Constant Declarations

Declarations keyword

Declarations Keyword

decoder

Memory Address Decoder

Decoders - Component Selection Guide

Design Flow Tutorial

Design Method - BINBCD

Design Method - BJACK

Design Method - MUXADD

Design Specification - BINBCD

Design Specification - BJACK

Design Specification - MUXADD

detailed descriptions

Pin-to-pin vs. Detailed Descriptions for Registered Designs
Detailed Example
Mixed Pin-to-pin and Detailed Example
Invert/Buffer Example

Detailed Designs

Detailed Circuit Descriptions
Detailed Descriptions: Designing for Macrocells
When to Use Detailed Descriptions
Examples of Pin-to-pin and Detailed Descriptions
Detailed Module with Inverted Outputs

device kits

Property Keyword

Device Programming - Downloading Your Design File

Device-independence

Device-independent ABEL-HDL Sources

devices

Device Keyword

Directives

@Standard - Standard Operators Directive
@Onset
@Ifiden - If Identical Directive
@Page - Page Directive
@Expr - Expression Directive
@Ifnb - If Not Blank Directive
@Radix - Default Base Numbering Directive
@Carry - Maximum Bit-width for Arithmetic Functions
@Repeat - Repeat Directive
@Ifndef - If Not Defined Directive
@Setsize - Set Indexing
@If - If Directive
@Ifniden - If Not Identical Directive
@Alternate - Alternate Operator Set
@Include - Include Directive
@Ifb - If Blank Directive
@Irp - Indefinite Repeat Directive
@Exit - Exit Directive
@Irpc - Indefinite Repeat, Character Directive
@Ifdef - If Defined Directive
@Message - Message Directive
Directives

division

Istype 'dc' - Unspecified Logic is Don't Care

Don't Care Set

@Dcset - Don't Care Set

don't cares

dot

Supported ABEL Dot Extensions

dot extensions

Feedbacks Specified Without Dot Extensions
Feedback Specification - .Q and .FB
Invert/Buffer Example
Pin-to-pin vs. Detailed Descriptions for Registered Designs

dummy arguments

Arguments and Argument Substitution

E

Else

When-Then-Else Keyword
If-Then-Else Keyword

Encoders - Component Selection Guide

End keyword

End Keyword

Entering T-Specs in a UCF file

equal

Relational Operators
Assignment Operators

Equation

Equation Blocks

Equation Examples

equations

Assignment Operators
How Equations Use Expressions

Equations keyword

Equations Keyword

example

Invert/Buffer Example
Detailed Example
Mixed Pin-to-pin and Detailed Example
Pin-to-Pin Example

expressions

How Equations Use Expressions
@Expr - Expression Directive
Expressions
Assignment Operators

extensions

Supported ABEL Dot Extensions

F

Fast and Slow Attribute in ABEL

feedback

Feedback Specification - .Q and .FB
State Diagram Feedback in Equations
Feedbacks Specified Without Dot Extensions
Feedback Normalization

Feedback Ambiguities

Resolving Feedback Ambiguities

Fitting

Using := for Alternative Flip-flop Types

Flip-flop Types

flip-flops

Feedback Specification - .Q and .FB

Flip-Flops - Component Selection Guide

Functional_block

Functional_block Keyword

Fuses keyword

Fuses Keyword

G

Goto keyword

Goto Keyword

greater than

Relational Operators

Grouping Signals

H

Help_CONTEXT

ABEL Syntax Reference

Hierarchical Designs

Interface Keyword (lower-level)
Interface - Declare Modules for Hierarchical Designs

Hierarchy

Hierarchy
Hierarchy and Test Vectors (PLD JEDEC Simulation)
Functional_block Keyword
Hierarchy and Retargeting and Fitting

I

Identifiers

If directives

@Ifdef - If Defined Directive
@Ifiden - If Identical Directive
@Ifniden - If Not Identical Directive
@Ifnb - If Not Blank Directive
@Ifb - If Blank Directive
@Ifndef - If Not Defined Directive
@If - If Directive

If-Then-Else keyword

If-Then-Else Keyword

Include

@Include - Include Directive

Indirectly Specifying tCO

Indirectly Specifying tSU

Input/Output Functions - Component Selection Guide

instantiation

Functional_block Keyword

Interface

Interface - Declare Modules for Hierarchical Designs
Interface Keyword (lower-level)
Interface Keyword (top-level)

Introduction to ABEL-HDL

inversion

Istype 'invert' - Inverter Attribute
Invert/Buffer Example
Istype 'invert' and 'buffer'

Istype

Istype 'invert' and 'buffer'
Istype 'reg_T' - T Flip-flop Clocked Memory Element
Istype 'xor' - XOR Gate in Target Device
Istype 'retain' - Do Not Minimize This Output
Invert/Buffer Example
Istype 'buffer' - Non-inverter attribute
Istype 'keep' - Do Not Collapse Signal
Istype 'collapse' - Collapse Combinational Node Attribute
Istype 'neg' - Unspecified Logic is 1
Istype 'dc' - Unspecified Logic is Don't Care
Istype 'pos' - Unspecified Logic is 0
Istype 'reg_JK' - JK Flip-flop Clocked Memory Element
Istype 'com' - Combinational Signal Attribute
Istype 'invert' - Inverter Attribute
Istype 'reg_SR' - SR Flip-flop Clocked Memory Element
Istype 'reg' - Clocked Memory Element
Istype 'reg_D' - D Flip-flop Clocked
Istype 'reg_G' - D Flip-flop Gated Clock Memory Element

Istype Attributes Overview

Istype Keyword

J

JEDEC simulation

Test_vectors Keyword

JK flip-flops

Istype 'reg_JK' - JK Flip-flop Clocked Memory Element

K

keywords

If-Then-Else Keyword
Interface Keyword (lower-level)
State_register Keyword
Device Keyword
Title Keyword
State Keyword (Declaration)
State Keyword (in State_diagram)
Test_vectors Keyword
State_diagram Keyword
Async_reset and Sync_reset
When-Then-Else Keyword
Library Keyword
Property Keyword
Xor_Factors Keyword
Pin Keyword
End Keyword
Interface Keyword (top-level)
Trace Keyword
Equations Keyword
Macro Keyword
Module Keyword
Goto Keyword
Case Keyword
Truth_Table Keyword
Functional_block Keyword
Node Keyword
With Keyword
Fuses Keyword

L

Language Structure

ABEL-HDL Source Structure

Latches - Component Selection Guide

less than

Relational Operators

Library keyword

Library Keyword

Locking Your Pinout

LogiBlox Functions

Logic Functions

logical operators

Building a Lower-level ABEL-HDL Source

Lower-level source

M

Macro keyword

Macro Keyword

Macrocells

Detailed Descriptions: Designing for Macrocells

Manual Pin Assignment Precautions

Memory Address Decoder

Merging Feedbacks

Miscellaneous Functions - Component Selection Guide

Module keyword

Module Keyword

modulus

multiplexer

12-to-4 Multiplexer

Multiplexers - Component Selection Guide

Multiplexing Output Signals vs 3-State Busses

multiplication

MUXADD Source File

N

Node Collapsing

Node keyword

Node Keyword

normalization of feedbacks

Feedback Normalization

NOT

Sequence of Evaluation
Relational Operators
Arithmetic Operators
Logical Operators
Range Operator
@Alternate - Alternate Operator Set
Operator Priority
Operators
Assignment Operators
@Standard - Standard Operators Directive

O

Open and Synthesize the jc2_abl Design

Open the jc2_abl Tutorial Project

operators

optimization

Istype 'collapse' - Collapse Combinational Node Attribute
Istype 'keep' - Do Not Collapse Signal
Istype 'retain' - Do Not Minimize This Output

Output Enable Control of Lower Level Modules

Output Enable Control of Lower Level Modules

P

PAL Conversion

Pin keyword

Pin Keyword

pin-to-pin descriptions

Pin-to-Pin Example
Pin-to-pin vs. Detailed Descriptions for Registered Designs
Mixed Pin-to-pin and Detailed Example

Pin-to-Pin Designs

Pin-to-Pin Language Features
Examples of Pin-to-pin and Detailed Descriptions

PLD JEDEC Simulation

Hierarchy and Test Vectors (PLD JEDEC Simulation)

PLD simulation

Test_vectors Keyword

powerup

preset

programmable output inversion

Set Indexing
Range Operator

Prohibiting Pin assignment in UCF file

Property keyword

Property Keyword

Q

R

Ranges

Redundant Nodes

Istype 'retain' - Do Not Minimize This Output

redundant product terms, retaining

registers

Pin-to-pin vs. Detailed Descriptions for Registered Designs

relational operators

Relational Operators

Repeat directives

@Irp - Indefinite Repeat Directive
@Irpc - Indefinite Repeat, Character Directive

Reserved Identifier (Keywords)

reset

Istype 'retain' - Do Not Minimize This Output

Retaining redundancy

Retargeting

Set Indexing
@Setsize - Set Indexing

S

Schematic Library - Component Selection Guide

Set indexing

Sets

Set Assignment and Comparison
Sets
Limitations/ Restrictions on Sets
Supported Set Operations
Set Operations
Set Indexing
Sequence of Evaluation

Setting Power Consumption in Design Manager

Setting Power Consumption in Project Navigator

Setting Pterms from Design Manager

Setting Pterms from Project Navigator

Setting Slew Rate in Design Manager

Setting Slew Rate in Project Navigator

shift

Istype 'reg_SR' - SR Flip-flop Clocked Memory Element

Shifters - Component Selection Guide

Simulating the Design

Source File

Sample Source File

Source File - BINBCD

Source File - BJACK

Specifiying tPD

Specifying fMAX

Specifying tCO

Specifying tSU

Speeding Up fMAX with Local Feedback

Speeding Up tCO with Local Feedback

Speeding Up tSU with Local Feedback

SR flip-flop

State

Using Symbolic State Machines

State (Declaration)

State Keyword (Declaration)

State (in State_diagram)

State Keyword (in State_diagram)

State Diagram

State Diagram Example

state diagrams

State Diagram Feedback in Equations
State_diagram Keyword

state machine

Blackjack Machine Operation
Combined Logic Descriptions
Blacjack Machine Description

State Machine Operation - BJACK

state machines

Async_reset and Sync_reset

State_register

State_register Keyword

subtraction

State_register Keyword
Using Symbolic State Machines

Supported ABEL Dot Extensions

Supported ASCII Characters

symbolic state machines

Sync_reset

Async_reset and Sync_reset

T

T flip-flops

Istype 'reg_T' - T Flip-flop Clocked Memory Element

Temporarily Ignoring Pin Assignments

test vectors

Trace Keyword
Hierarchy and Test Vectors (PLD JEDEC Simulation)
Test_vectors Keyword

Test Vectors - BINBCD

Test Vectors - BJACK

Test Vectors - MUXADD

The Xilinx WEB Site

Then

If-Then-Else Keyword
When-Then-Else Keyword

Title keyword

Title Keyword

Top-level Source

Building a Top-level ABEL-HDL Source

Trace keyword

Trace Keyword

transition statements

Equation Blocks

Truth Table Examples

Truth_Table

Trace Keyword

Truth_Table keyword

Truth_Table Keyword

twos complement

Istype 'pos' - Unspecified Logic is 0
Istype 'neg' - Unspecified Logic is 1

U

unspecified logic

Using Global Nets

Using Intermediate Expressions

Using Timing Constraint Driven Optimization

Using XC9500 Local Function Block Feedback

V

W

When-Then-Else keywords

When-Then-Else Keyword

With keyword

With Keyword

X

Xilinx ABEL Property Statements

xilinx property BUFG

xilinx property FAST

xilinx property INIT

xilinx property LOC

xilinx property PWR_MODE

xilinx property SLOW

Xilinx Property TNM

XNOR