CPLD Attributes Used in Schematics

BUFG=CLK|OE|SR on an IBUF symbol or its input net (the pad net).
(Assigns global buffers to internal nets or to input pins in a top-level design. CLK=Global Clock, OE=Global Output Enable, SR=Global Set/Reset)

COLLAPSE on a logic symbol or its output net.
(Forces a logic mode to be collapsed into all of its fanouts.)

FAST | SLOW on an OBUF, OBUFE or OBUFT type symbol or its output net (the pad net).
(Selects output slew rate for output pins in top-level design.)

INIT=R|S on a flip-flop or other registered macro symbol or its output net.
(Defines initial state of registers.)

KEEP on a logic symbol or its output net.
(Preserves internal nodes during design implementation.)

LOC=Ppin_number|BGA_pin_name [eg. LOC=P23, LOC=AC17] on any pad or pad net.
(Assigns a device pin number to an input or output pad of the design.)

LOC=FBnn [eg. LOC=FB3] on a logic symbol or its output net, or on an output pad or the pad's net.
(Assigns an internal Function Block number to logic driving an internal node or device output; typically used only to control XC9500 local feedback routing.)

NOREDUCE on a logic symbol or its output net.
(Preserves redundant logic terms during design implementation.)

PROHIBIT on unused device pins allows you to reserve the pins for later use, or simply to prevent them from being used at all.

PWR_MODE=LOW|STD on a logic symbol or its output net.
(Selects macrocell power mode for nodes or outputs in CPLD designs.)

REG=CE|TFF on a FDCE or FDPE primitive or its output net.
(REG=CE forces the CE pin to be implemented using the clock enable product term of the XC9500XL or XC9500XV macrocell. REG=CE attributes are ignored for XC9500 macrocells. REG=TFF indicates that the register is to be implemented with a T-type-flip-flop. REG=TFF on a D-type-flip-flop will cause the D-input expression to be converted to a T-input expression.)

TNM=group_name [eg. TNM=MY_GROUP1] on any pad, flip-flop symbol or any net.
(Tags signals with a Timing-group Name to be used in a Timespec.)

TSnn=FROM:source_group:TO:dest_group:delay
[eg. TS02=FROM:PADS(IBUS*):TO:MY_GROUP1:16] on a TIMESPEC symbol.
(Defines a point-to-point timing constraint.)

TSnn=PERIOD:clock_group:delay [eg. TS10=PERIOD:CLK1_GRP:12] on a TIMESPEC symbol.
(Defines a clock period timing constraint.)