Specifying Clock Enable Manually in VHDL and Verilog

For VHDL and Verilog designs, apply the REG=CE attribute to the output net of a FDCE or FDPE primitive using the following syntax in a UCF file:

NET net_name REG=CE;

When assigning attributes to bus (vector) elements, the name generated in the netlist will be the bus name and subscript seperated by an underscore. For example if the design contined a bus Q with subsripts 3 downto 0, then you would use Q_3 as the net name in the UCF to assign an attribute to subscript 3 of Q.