Assigning Pins in VHDL or Verilog

In VHDL or Verilog designs, assign pins to a net in the UCF file using the following syntax:

For PC, PQ, TQ, and similar packages, specify the numeric pin number starting with a P.

NET net_name LOC=Ppin_number;

For CS, BG, and similar packages, specify the alphanumeric pin name to an input or output pad of the design .

NET net_name LOC=pin_name;

When assigning pin locations to bus (vector) elements, the name generated in the netlist will be the bus name and subscript seperated by an underscore. For example if the design contined a bus Q with subsripts 3 downto 0, then you would use Q_3 as the net name in the UCF to assign a pin location to subscript 3 of Q.