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:= - Assignment Operator
?:= - Assignment Operator
?= - Assignment Operator
@DCState
@directive
@Setsize - Set Indexing
@Ifb - If Blank Directive
@Ifdef - If Defined
Directive
@Ifiden
- If Identical Directive
@Ifnb
- If Not Blank Directive
@Ifndef
- If Not Defined Directive
Directives
@Alternate -
Alternate Operator Set
@Standard
- Standard Operators Directive
@Ifniden
- If Not Identical Directive
@Const
- Constant Declarations
@Include
- Include Directive
@Exit
- Exit Directive
@Irp
- Indefinite Repeat Directive
@If
- If Directive
@Irpc
- Indefinite Repeat, Character Directive
@Carry
- Maximum Bit-width for Arithmetic Functions
@Repeat
- Repeat Directive
@Message
- Message Directive
@Expr
- Expression Directive
@Onset
@Dcset - Don't Care Set
@Page - Page Directive
@Radix - Default
Base Numbering Directive
=
= - Assignment Operator
4-Bit Comparator
4-Bit Universal Counter
ABEL
ABEL Design Examples
ABEL Design Flow
ABEL-HDL
ABEL-HDL Design Considerations
ABEL-HDL language
Functional_block Keyword
Interface Keyword
(lower-level)
Interface
- Declare Modules for Hierarchical Designs
ABEL
Syntax Reference
Interface
Keyword (top-level)
ABEL-HDL Reference
ABEL-HDL Sources
adders
addition
AND
Application Error -- Call to Undefined Dynalink
Arguments
arithmetic functions
Arithmetic Functions - Component Selection Guide
arithmetic operators
Assigning Global Nets in Design Manager
Assigning Global Nets in Project Navigator
Assigning Global Nets Manually in ABEL
Assigning Pins in ABEL
Assigning Pins Manually
assignment operators
Async_reset
attributes
Istype 'com'
- Combinational Signal Attribute
Istype
'keep' - Do Not Collapse Signal
Istype
'neg' - Unspecified Logic is 1
Istype
'pos' - Unspecified Logic is 0
Istype
'xor' - XOR Gate in Target Device
Istype
'buffer' - Non-inverter attribute
Istype
'collapse' - Collapse Combinational Node Attribute
Istype
'dc' - Unspecified Logic is Don't Care
Istype
'invert' - Inverter Attribute
Istype
'reg' - Clocked Memory Element
Istype
'reg_D' - D Flip-flop Clocked
Istype
'reg_G' - D Flip-flop Gated Clock Memory Element
Istype
'reg_JK' - JK Flip-flop Clocked Memory Element
Istype
'reg_SR' - SR Flip-flop Clocked Memory Element
Istype
'reg_T' - T Flip-flop Clocked Memory Element
Istype
'retain' - Do Not Minimize This Output
base numbering
Basic Syntax
Blacjack Machine Description
black box designs
Blackjack Machine - BINBCD
Blackjack Machine - BJACK
Blackjack Machine - MUXADD PLD
Blackjack Machine Implementation
Blackjack Machine Operation
Blocks
buffer
Buffers and Inverters - Component Selection Guide
carry logic
Case keyword
Choosing Identifiers
Clocked Memory Element
Istype 'reg_JK'
- JK Flip-flop Clocked Memory Element
Istype
'reg_G' - D Flip-flop Gated Clock Memory Element
Istype
'reg_SR' - SR Flip-flop Clocked Memory Element
Istype
'reg_D' - D Flip-flop Clocked
Istype
'reg_T' - T Flip-flop Clocked Memory Element
Istype
'reg' - Clocked Memory Element
collapse
combinational nodes
Combinational Signal
Combined Logic Descriptions
Comments
comparator
comparators
Comparators - Component Selection Guide
Constant Declarations
Constants
Controlling Initial States in ABEL
Controlling Logic Optimization
Controlling Power Consumption
Controlling Power Consumption in ABEL
Controlling Register Initial States
Controlling Slew Rate
Copyright and Trademark Information
counter
counters
Counters - Component Selection Guide
CPLD Application Notes
CPLD Attributes
CPLD Attributes Used in a User Constraints File (UCF)
CPLD Attributes Used in ABEL Files
CPLD Attributes Used in Schematics
CPLD Design Techniques
Creating Bidirectional Signals
Creating Counters
Creating Latches
Creating Read-Back Registers
D Flip-flop
declarations
Declarations keyword
decoder
Decoders - Component Selection Guide
Design Flow Tutorial
Design Method - BINBCD
Design Method - BJACK
Design Method - MUXADD
Design Specification - BINBCD
Design Specification - BJACK
Design Specification - MUXADD
detailed descriptions
Pin-to-pin
vs. Detailed Descriptions for Registered Designs
Detailed
Example
Mixed
Pin-to-pin and Detailed Example
Invert/Buffer
Example
Detailed Designs
Detailed Circuit
Descriptions
Detailed
Descriptions: Designing for Macrocells
When
to Use Detailed Descriptions
Examples
of Pin-to-pin and Detailed Descriptions
Detailed
Module with Inverted Outputs
device kits
Device Programming - Downloading Your Design File
Device-independence
devices
Directives
@Standard
- Standard Operators Directive
@Onset
@Ifiden - If Identical
Directive
@Page -
Page Directive
@Expr
- Expression Directive
@Ifnb
- If Not Blank Directive
@Radix
- Default Base Numbering Directive
@Carry
- Maximum Bit-width for Arithmetic Functions
@Repeat
- Repeat Directive
@Ifndef
- If Not Defined Directive
@Setsize
- Set Indexing
@If -
If Directive
@Ifniden
- If Not Identical Directive
@Alternate
- Alternate Operator Set
@Include
- Include Directive
@Ifb
- If Blank Directive
@Irp
- Indefinite Repeat Directive
@Exit
- Exit Directive
@Irpc
- Indefinite Repeat, Character Directive
@Ifdef
- If Defined Directive
@Message
- Message Directive
Directives
division
Don't Care Set
don't cares
dot
dot extensions
Feedbacks
Specified Without Dot Extensions
Feedback
Specification - .Q and .FB
Invert/Buffer
Example
Pin-to-pin
vs. Detailed Descriptions for Registered Designs
dummy arguments
Else
Encoders - Component Selection Guide
End keyword
Entering T-Specs in a UCF file
equal
Equation
Equation Examples
equations
Equations keyword
example
expressions
extensions
Fast and Slow Attribute in ABEL
feedback
Feedback Specification
- .Q and .FB
State
Diagram Feedback in Equations
Feedbacks
Specified Without Dot Extensions
Feedback
Normalization
Feedback Ambiguities
Fitting
Flip-flop Types
flip-flops
Flip-Flops - Component Selection Guide
Functional_block
Fuses keyword
Goto keyword
greater than
Grouping Signals
Help_CONTEXT
Hierarchical Designs
Hierarchy
Hierarchy
Hierarchy
and Test Vectors (PLD JEDEC Simulation)
Functional_block
Keyword
Hierarchy
and Retargeting and Fitting
Identifiers
If directives
@Ifdef - If Defined
Directive
@Ifiden
- If Identical Directive
@Ifniden
- If Not Identical Directive
@Ifnb
- If Not Blank Directive
@Ifb
- If Blank Directive
@Ifndef
- If Not Defined Directive
@If
- If Directive
If-Then-Else keyword
Include
Indirectly Specifying tCO
Indirectly Specifying tSU
Input/Output Functions - Component Selection Guide
instantiation
Interface
Interface
- Declare Modules for Hierarchical Designs
Interface
Keyword (lower-level)
Interface
Keyword (top-level)
Introduction to ABEL-HDL
inversion
Istype
Istype 'invert' and
'buffer'
Istype
'reg_T' - T Flip-flop Clocked Memory Element
Istype
'xor' - XOR Gate in Target Device
Istype
'retain' - Do Not Minimize This Output
Invert/Buffer
Example
Istype
'buffer' - Non-inverter attribute
Istype
'keep' - Do Not Collapse Signal
Istype
'collapse' - Collapse Combinational Node Attribute
Istype
'neg' - Unspecified Logic is 1
Istype
'dc' - Unspecified Logic is Don't Care
Istype
'pos' - Unspecified Logic is 0
Istype
'reg_JK' - JK Flip-flop Clocked Memory Element
Istype
'com' - Combinational Signal Attribute
Istype
'invert' - Inverter Attribute
Istype
'reg_SR' - SR Flip-flop Clocked Memory Element
Istype
'reg' - Clocked Memory Element
Istype
'reg_D' - D Flip-flop Clocked
Istype
'reg_G' - D Flip-flop Gated Clock Memory Element
Istype Attributes Overview
Istype Keyword
JEDEC simulation
JK flip-flops
keywords
If-Then-Else Keyword
Interface Keyword
(lower-level)
State_register
Keyword
Device Keyword
Title Keyword
State
Keyword (Declaration)
State
Keyword (in State_diagram)
Test_vectors
Keyword
State_diagram
Keyword
Async_reset
and Sync_reset
When-Then-Else
Keyword
Library Keyword
Property Keyword
Xor_Factors
Keyword
Pin Keyword
End Keyword
Interface
Keyword (top-level)
Trace
Keyword
Equations Keyword
Macro Keyword
Module
Keyword
Goto Keyword
Case Keyword
Truth_Table
Keyword
Functional_block
Keyword
Node Keyword
With Keyword
Fuses
Keyword
Language Structure
Latches - Component Selection Guide
less than
Library keyword
Locking Your Pinout
LogiBlox Functions
Logic Functions
logical operators
Lower-level source
Macro keyword
Macrocells
Manual Pin Assignment Precautions
Memory Address Decoder
Merging Feedbacks
Miscellaneous Functions - Component Selection Guide
Module keyword
modulus
multiplexer
Multiplexers - Component Selection Guide
Multiplexing Output Signals vs 3-State Busses
multiplication
MUXADD Source File
Node Collapsing
Node keyword
normalization of feedbacks
NOT
Open and Synthesize the jc2_abl Design
Open the jc2_abl Tutorial Project
operators
Sequence of
Evaluation
Relational
Operators
Arithmetic
Operators
Logical Operators
Range Operator
@Alternate
- Alternate Operator Set
Operator
Priority
Operators
Assignment
Operators
@Standard
- Standard Operators Directive
optimization
Istype 'collapse'
- Collapse Combinational Node Attribute
Istype
'keep' - Do Not Collapse Signal
Istype
'retain' - Do Not Minimize This Output
OR
Output Enable Control of Lower Level Modules
PAL Conversion
Pin keyword
pin-to-pin descriptions
Pin-to-Pin Example
Pin-to-pin vs.
Detailed Descriptions for Registered Designs
Mixed
Pin-to-pin and Detailed Example
Pin-to-Pin Designs
PLD JEDEC Simulation
PLD simulation
powerup
preset
programmable output inversion
Prohibiting Pin assignment in UCF file
Property keyword
Ranges
Redundant Nodes
redundant product terms, retaining
registers
relational operators
Repeat directives
Reserved Identifier (Keywords)
reset
Retaining redundancy
Retargeting
Schematic Library - Component Selection Guide
Set indexing
Sets
Set Assignment
and Comparison
Sets
Limitations/
Restrictions on Sets
Supported
Set Operations
Set Operations
Set Indexing
Sequence
of Evaluation
Setting Power Consumption in Design Manager
Setting Power Consumption in Project Navigator
Setting Pterms from Design Manager
Setting Pterms from Project Navigator
Setting Slew Rate in Design Manager
Setting Slew Rate in Project Navigator
shift
Shifters - Component Selection Guide
Simulating the Design
Source File
Source File - BINBCD
Source File - BJACK
Specifiying tPD
Specifying fMAX
Specifying tCO
Specifying tSU
Speeding Up fMAX with Local Feedback
Speeding Up tCO with Local Feedback
Speeding Up tSU with Local Feedback
SR flip-flop
State
State (Declaration)
State (in State_diagram)
State Diagram
State Diagram Example
state diagrams
state machine
State Machine Operation - BJACK
state machines
State_register
subtraction
Supported ABEL Dot Extensions
Supported ASCII Characters
symbolic state machines
Sync_reset
T flip-flops
Temporarily Ignoring Pin Assignments
test vectors
Test Vectors - BINBCD
Test Vectors - BJACK
Test Vectors - MUXADD
The Xilinx WEB Site
Then
Title keyword
Top-level Source
Trace keyword
transition statements
Truth Table Examples
Truth_Table
Truth_Table keyword
twos complement
unspecified logic
Using Global Nets
Using Intermediate Expressions
Using Timing Constraint Driven Optimization
Using XC9500 Local Function Block Feedback
When-Then-Else keywords
With keyword
Xilinx ABEL Property Statements
xilinx property BUFG
xilinx property FAST
xilinx property INIT
xilinx property LOC
xilinx property PWR_MODE
xilinx property SLOW
Xilinx Property TNM
XNOR
XOR
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