CPLD Attributes Used in a User Constraints File (UCF)
INST inst_name BUFG=CLK|OE|SR; on an IBUF or internal symbol.
or
NET net_name BUFG=CLK|OE|SR;
on an internal or input pad net.
(Assigns global buffers to internal nets or input
pins in a top-level design.)
INST inst_name COLLAPSE; on a logic symbol.
or
NET net_name COLLAPSE;
on a logic net.
(Forces a logic mode to be
collapsed into all of its fanouts.)
INST inst_name FAST | SLOW; on an OBUF, OBUFE or OBUFT
type symbol.
or
NET net_name FAST | SLOW;
on an output pad net.
(Selects output slew rate for
output pins in top-level design.)
INST inst_name INIT=R|S; on a flip-flop or other
registered macro symbol.
or
NET net_name INIT=R|S;
on the output net of a flip-flop or other registered macro symbol.
(Defines initial state of registers.)
INST inst_name KEEP; on a logic symbol.
or
NET net_name KEEP;
on a logic net.
(Preserves internal nodes during
design implementation.)
NET net_name LOC=Ppin_number on any pad net.
(Assigns a device pin number to an
input or output pad of the design for
PC, PQ, VQ, TQ packages.)
NET net_name LOC=pin_name;
on any pad net.
(Assigns an alphanumeric pin name
to an input or output pad of the design for CS, BG packages.)
INST inst_name LOC=FBnn; [eg. INST U3 LOC=FB3;] on
a logic symbol.
or
NET net_name LOC=FBnn;
on a logic net or an output pad net.
(Assigns an internal Function Block
number to logic driving an internal node or device output; typically
used only to control XC9500 local feedback routing.)
INST inst_name NOREDUCE; on a logic symbol.
or
NET net_name NOREDUCE;
on a logic net.
(Preserves redundant logic terms
during design implementation.)
NET net_name OFFSET=IN:delay:BEFORE:clock_net_name;
on an input pad net.
(Defines an input pad setup time
constraint before the active edge of the named clock input pad.)
NET net_name OFFSET=OUT:delay:AFTER:clock_net_name;
on an output pad net.
(Defines a clock-pad-to-output-pad
propagation delay timing constraint.)
INST inst_name PWR_MODE=LOW|STD; on a logic symbol.
or
NET net_name PWR_MODE=LOW|STD;
on a logic net.
(Selects macrocell power mode for
nodes or outputs in CPLD designs.)
INST inst_name REG=CE|TFF; on a FDCE or FDPE primitive.
or
NET net_name REG=CE|TFF;
on a FDCE or FDPE primitive logic net.
(REG=CE forces the CE pin to be implemented using the clock enable product
term of the XC9500XL or XC9500XV macrocell. REG=CE attributes are ignored for XC9500 macrocells. REG=TFF
indicates that the register is to be implemented with a T-type-flip-flop. REG=TFF on a D-type-flip-flop will
cause the D-input expression to be converted to a T-input expression.)
INST inst_name TNM=group_name; [eg. INST FLOP1
TNM=MY_GROUP1;] on any flip-flop symbol.
or
NET net_name TNM=group_name;
on any logic net or pad net.
(Tags signals with a Timing-group
Name to be used in a Timespec.)
TIMESPEC TSnn=FROM:source_group:TO:dest_group:delay;
[eg. TIMESPEC TS02=FROM:PADS(IBUS*):TO:MY_GROUP1:16;].
(Defines a point-to-point timing constraint.)
TIMESPEC TSnn=PERIOD:clock_group:delay; [eg.
TIMESPEC TS10=PERIOD:CLK1_GRP:12;].
(Defines a clock period timing constraint.)
CONFIG PROHIBIT=pin_name...;
(Defines one or more pin locations on the device that should remain unused.)