CPLD Attributes Used in ABEL Files

ISTYPE 'KEEP'
(Preserves internal nodes in both ABEL compiler and design implementation.)

ISTYPE 'RETAIN'
(Preserves redundant logic terms in both ABEL and design implementation.)

XILINX PROPERTY 'FAST | SLOW output_pin...';
(Selects output slew rate for output pins in top-level XABEL design.)

XILINX PROPERTY 'BUFG=CLK | OE | SR input_pin...';
(Assigns global buffers to internal nets or to input pins in a top-level XABEL design.)

XILINX PROPERTY 'INIT=R | S reg_signal...';
(Defines initial state of registers.)

XILINX PROPERTY 'PWR_MODE=LOW | STD signal_name...';
(Selects macrocell power mode for nodes or outputs in CPLD designs.)

XILINX PROPERTY 'REG=CE | TFF reg_signal...';
(REG=CE forces the CE pin to be implemented using the clock enable product term of the XC9500XL or XC9500XV macrocell. REG=CE attributes are ignored for XC9500 macrocells. REG=TFF indicates that the register is to be implemented with a T-type-flip-flop. REG=TFF on a D-type-flip-flop will cause the D-input expression to be converted to a T-input expression.)

XILINX PROPERTY 'TNM=group_name signal_name...';
(Tags registered signals with a Timing-group name to be used in a Timespec.)