Creating Latches

You can create registered latches that use the macrocell register set and reset product terms or combinatorial latches that use sum-term logic and feedback loops.

Registered latches use fewer resources than combinatorial latches when the data being latched and the latch enable signal generate only single product term set and reset functions as shown below:

The following examples show how to create latches:

Creating Latches in ABEL

Creating Latches in VHDL

Creating Latches in Verilog