Creating Read-Back Registers

This example shows how to implement a simple read-back register. Data is written from the I/O pad to the register on the rising edge of clock if READ_ENABLE is inactive and WRITE_ENABLE is active. Data is read from the I/O pad when READ_ENABLE is active. The following drawing shows how the code is implemented in the device:

ABEL Example

VHDL Example

Verilog Example