Detailed Module with Inverted Outputs

module Q1_3
Q1 pin istype 'reg_D,invert';
Clock,Preset pin;

equations
Q1.CLK = Clock;
!Q1.D = Q1.Q # Preset;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

In this version of the module, the existence of an inverter between the output of the D-type flip-flop and the output pin (specified with the 'invert' attribute) has necessitated a change in the equation for Q1.D.

As this example shows, using device independence and pin-to-pin description methods is desirable, since you can describe a circuit completely for any implementation. Using pin-to-pin descriptions and generalized dot extensions (such as .FB, .CLK and .OE) as much as possible allows you to implement your ABEL-HDL module into any one of a particular class of devices. (For example, any device that features enough flip-flops and appropriately configured I/O resources.) However, the need for particular types of device features (such as register preset or reset) might limit your ability to describe your design in a completely architecture-independent way.

If, for example, a built-in register preset feature is used in a simple design, the target architectures are limited. Consider this version of the design:

module Q1_5
Q1 pin istype 'reg,buffer';
Clock,Preset pin;

equations
Q1.CLK = Clock;
Q1.AP = Preset;
Q1 := !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

The equation for Q1 still uses the := assignment operator and .FB for a pin-to-pin description of Q1's behavior, but the use of .AP to describe the reset function requires consideration of different device architectures. The .AP extension, like the .D and .Q extensions, is associated with a flip-flop input, not with a device output pin. If the target device has inverted outputs, the design will not reset properly, so this ambiguous reset behavior is removed by using the 'buffer' attribute, with the result of reducing the number of devices for the design to those that feature non-inverted outputs.

Using .ASET instead of .AP can solve this problem if the fitter being used supports the .ASET dot extension.

The versions 5 and 7 of the design above and below are unambiguous, but each is restricted to certain classes of devices:

module Q1_7
Q1 pin istype 'reg,invert';
Clock,Preset pin;

equations
Q1.CLK = Clock;
Q1.AR = Preset;
Q1 := !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end