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Hierarchy and Retargeting

Redundant Nodes

When you link multiple sources, some redundant nodes may be generated. These nodes usually originate from lower-level outputs that are not being used in the top-level source. For example, when you use a 4-bit counter as a 3-bit counter. The most significant bit of the counter is unused and can be removed from the design to save device resources.

Merging Feedbacks

Linking multiple modules can produce signals with one or more feedback types, such as .FB and .Q. You can tell the optimizer to combine these feedbacks to help the fitting process.

Post-linked Optimization

If your design has a constant tied to an input, you can re-optimize the design. Re-optimizing may further reduce the product terms count. For example, if you have the equation

out = i0 & i1 || !i0 & i2;

and i0 is tied to 1, the resulting equation would be simplified to

out = i1;


See Also

Hierarchy and Test Vectors (PLD JEDEC Simulation)

Node Collapsing

Building a Top-level ABEL-HDL Source

Building a Lower-level ABEL-HDL Source