Introduction to ABEL-HDL

ABEL-HDL is a hardware description language that supports a variety of behavioral input forms, including high-level equations, state diagrams, and truth tables. The ABEL and Synario versions of the ABEL-HDL compiler (and supporting software) functionally verify ABEL-HDL designs through simulation. The compilers then implement the designs in PLDs or FPGAs. ABEL-HDL designs can also be transferred to other design environments through standard-format design transfer files.

You can enter designs in ABEL-HDL and verify them with little or no concern for the architecture of the target device.

Architecture-independent design descriptions (those that do not include device declarations and pin number declarations) require more comprehensive descriptions than their architecture-specific counterparts. Assumptions that can be made when a particular device is specified are not possible when no device is specified.