Invert/Buffer Example

The test vectors in the following two designs illustrate how the 'invert' attribute complements output signals with detailed dot extensions (.D, .T, .S, .R., .J., and .K).

module buffer
q0,q1 pin istype 'reg,buffer';
clock pin;
reset pin;

equations
[q1,q0].clk = clock;
[q1.D,q0.D] = [q1.Q,q0.Q] + 1;
[q1.SR,q0.SR] = reset;

test vectors
([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 0, 0];
end

module invert
q0,q1 pin istype 'reg,invert';
clock pin;
reset pin;

equations
[q1,q0].clk = clock;
[q1.D,q0.D] = ([q1.Q,q0.Q] + 1);
[q1.SR,q0.SR] = reset;

test vectors
([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 1, 1];
[ .c., 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 1 ]->[ 1, 1];
end

The 'invert' declaration in the second design results in inverted outputs and in an inverted reset function.