State_diagram Keyword

Syntax

STATE_DIAGRAM state_reg
[-> state_out]
STATE state_exp : [equation]
[equation]
:
:
trans_stmt ;]

state_reg - An identifier or set of identifiers specifying the signals that determine the current state of the machine.

state_out - An identifier or set of identifiers that determine the next state of the machine (for designs with external registers).

state_exp - An expression giving the current state.

equation - A valid equation that defines the state machine outputs.

trans_stmt - An IF-THEN-ELSE, CASE, or GOTO statement, optionally followed by WITH transition equations.

Use

The state description describes the operation of a sequential state machine implemented with programmable logic. You can use state descriptions to describe logic as an alternative to Boolean equations or truth tables.

Example

The following is an example of a simple state machine that advances from one state to the next, setting the output to the current state, and then starting over again. Note that the states do not need to be specified in any particular order. Note also that state 2 is identified by an expression rather than by a constant. The state register is composed of the signals a and b.

state_diagram [a,b]

state 3: y = 3 ;
goto 0 ;

state 1: y = 1 ;
goto S2 ;

state 0: y = 0 ;
goto 1 ;

state S2; y = S2 ;
goto 3 ;