Verilog - Stimulus Block

module counter_test(clrd, fd, ind, clkd);

input clkd;

output clrd;

output [1:0] fd;

output [7:0] ind;

reg clrd;

reg [1:0] fd;

reg [7:0] ind;

clock_gen #(100, 50) clockd(clkd);

always @(posedge clkd) begin

clrd=1; fd=0; ind=0;

#100 clrd=1; fd=0; ind=0;

#100 clrd=0; fd=0; ind=8’b01010101;

#100 clrd=0; fd=3; ind=8’b11111111;

#100 clrd=0; fd=1; ind=8’b10101010;

#100 clrd=0; fd=2; ind=8’b11001100; end

endmodule

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