FSM VHDL Code - Enumerated Data Type

Enumerated data type

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

USE ieee.std_logic_arith.all;

ENTITY state_m2 IS

PORT(clk, reset, nw : in std_logic;

sel: out std_logic_vector(1 downto 0);

nxt, first: out std_logic);

END state_m2;

ARCHITECTURE logic OF state_m2 IS

TYPE state_type IS

(idle, tap1, tap2, tap3, tap4);

SIGNAL filter : state_type;