This section covers cable connection to the target device. You need appropriate pins on the target system for connecting the target system board to the header connectors on the cable.
WARNINGThe cable draws its power from the target system through VCC and GND. Therefore, power to the cable, as well as to the target FPGA, must be stable. Do not connect any signals before connecting VCC and GND. The input/output pins of the internal XChecker FPGA should always be at a potential that is lower or equal to their respective rail voltage in order to avoid internal damage.
Connect all the pins of your serial or parallel cable for downloading using the guidelines in the “XChecker Operation Mode Connections” table and the “Cable Connections and Definitions” table.
The XChecker cable supports two types of connectors. You can connect to the pins of your target FPGA with a flying lead connector and to the FPGA demonstration boards with a header connector.
For each type of connector, there are two different subconnectors. One is keyed for the downloading signals; the second is keyed for readback signals. Header 1 is the download subconnector and fits on the outermost subconnector socket. Header 2 is the readback subconnector and fits on the inner subconnector socket.
Refer to the tables in this section for information on how to connect the signal pins for specific applications. The “XChecker Operation Mode Connections” table shows the necessary connections for each application type, and the “Cable Connections and Definitions” table describes the pins and how to connect them.
Not all of the signal pins are required for each function.
| Cable Header | Pin Name | Download | Verification | Synchronous Logic Probe | Asynchronous Logic Probe |
|---|---|---|---|---|---|
| 1 | VCC | X | X | X | X |
| 1 | GND | X | X | X | X |
| 1 | CCLK | X | X | X | X |
| 1 | D/P | X | |||
| 1 | DIN | X | |||
| 1 | PROG (XC4000 only) | X | |||
| 1 | INIT (XC3000/XC4000 only) | X | |||
| 1 | RST | Opt | Opt | Opt | Opt |
| 2 | RT | X | X | X | |
| 2 | RD | X | X | X | |
| 2 | TRIG | Opt | Opt | ||
| 2 | TDI | ||||
| 2 | TCK | ||||
| 2 | TMS | ||||
| 2 | CLKI | Opt | |||
| 2 | CLKO | X | |||
| X = Connect as specified in the “Cable Connections and Definitions” table. Opt = Optional | |||||
| Signal Name | Function | XC3000 | XC4000 | XC5200 |
|---|---|---|---|---|
| VCC | Power - Supplies VCC to cable (5 V, 100 mA, typically) | Connect to target system. | ||
| GND | Ground - Supplies ground reference to cable | Connect to target system ground. | ||
| CCLK | Configuration Clock - Provides configuration clock to target system during configuration and readback | Connect to target system Configuration Clock. Ensure all devices are in slave serial mode if using download cable to download. | ||
| D/P | Done/Program - Signals the end of configuration (For XC3000 devices, a High-to-Low transition on D/P coupled with a High to Low on Reset, causes the device to reprogram.) | Connect to D/!P pin with a 10-50 kilohm pull-up resistor. | Connect to target system DONE pin and rely on internal 2-8 kilohm pull-up resistors. | |
| DIN | Data In - Provides configuration data to target system during configuration and is tristated at all other times | Connect to target system's lead device DIN pin. | ||
| PROG (XC4000 Only) | Program - 300ns or greater Low pulse causes device to reprogram (A Low indicates the device is clearing its configuration memory.) | N/A | Connect to target system !PROG with 10-50 kilohm pull-up resistor. | |
| INIT | Initialize - Indicates start of configuration for XC3000/XC4000 parts. A logical zero on this pin during configuration indicates a data error | Connect to target system INIT with a 10-50 kilohm pull-up resistor. | ||
| RST | Reset - During configuration, a Low pulse causes XC3000A devices to restart configuration After configuration, this pin can drive Low to reset target FPGA internal latches and flip-flops RST is the active high for XC4000/XC5200 devices | Connect to target FPGA !RESET pin with 10-50 kilohm pull-up resistor. | User-programmable connection; requires a 10-50 kilohm pull-up resistor | |
| RT | Read Trigger - XChecker output Hardware Debugger provides Low-to-High transition on RT to initiate readback | Connect to M0/RTRIG with 10-50 kilohm pull-up resistor. | User-programmable connection; requires 10-50 kilohm pull-up resistor | |
| RD | Read Data - XChecker input Hardware Debugger receives the readback data through the RD pin after readback is initiated. | Connect to M1/RDATA through pull-up resistor in slave serial configuration mode; requires a 10-50 kilohm pull-up resistor if using I/O pad as input or output | User-programmable connection; requires 10-50 kilohm pull-up resistor if using I/O pad as input or output | |
| TRIG | System Trigger - XChecker input High on this pin signals the XChecker electronics to initiate a readback and causes the RT pin to go High | Connect to target system readback trigger and to an external pin if using an external signal to trigger readback. | ||
| TDI TCK TMS | Reserved (These pins can be used for JTAG Programmer device configuration.) | N/A | ||
| CLKI | Clock Input - Transmits your system clock to the XChecker electronics Clock must be between 120 kHz and 10 MHz Connect this pin to target system clock to synchronize the readback trigger with target system clock | Connect to source of target system clock for synchronous debugging. | ||
| CLKO | Clock Output - Drives target system clock Clock can come from either the CLKI pin, or it can be internally generated by the XChecker cable when CLKI is unconnected | Connect to destination of target system clock for synchronous debugging. | ||
XChecker does not drive the configuration mode pins (M0, M1, M2) during configuration. You must specify the logic levels for these pins externally.
If you are using a 3 V target board instead of a 5 V target board, you must connect the 3 V adapter to the XChecker cable. The 3 V adapter supports VCC supply voltages from your target system that range from 2.9 V to 5.25 V. An internal voltage “step-up” circuit generates the 5 V voltage supply needed by the XChecker cable.
Aside from the voltage conversion, the 3 V adapter is completely transparent to the XChecker hardware and the target system. Therefore, you do not need to remove the 3 V adapter when moving the XChecker cable between 3 V and 5 V systems.
The 3 V adapter includes two connectors, J1 and J2.
For information on testing the operation of the 3 V adapter, see the “Testing 3 V Adapter Operation” section.
Follow these steps to connect the 3 V adapter to the XChecker cable.
WARNINGUse standard electrostatic discharge (ESD) precautions when connecting the adapter to your XChecker cable. The adapter is static sensitive and can be damaged by ESD energy.
Figure 4.3 3 V Adapter Connected to XChecker Cable |  |
To use the 3 V adapter with XC3000L and XC4000XL parts, follow these steps.
The configuration of the XC3000L devices is the same as the XC3000, XC3000A, and XC3100 devices.
The readback clock speed of the XC3000L devices has been slowed because of lower VCC supply voltage. If the supply voltage of the target system is lower than 3 V, you might see an error message similar to the one shown below.
XCHECKER? verify
Design design_name has 128 probeable signals.
Readback 1847 bytes of configuration.
Verifying datafile design_name...MISMATCHED Total of 405 bits mismatched.
To connect your cable for downloading only, connect your configuration cable to your target FPGA device. Refer to the “XChecker Operation Mode Connections” table and the “Cable Connections and Definitions” table for pin assignment information. The “Downloading Configuration Data” figure shows the XChecker cable connected for downloading only.
Figure 4.4 Downloading Configuration Data | |
To connect your cable for downloading and verification, connect your XChecker cable to your target FPGA as shown in the “XChecker Cable Connections for Downloading and Verification” figure. Refer to the “XChecker Operation Mode Connections” table for pin assignment information.
Figure 4.5 XChecker Cable Connections for Downloading and Verification | |
You can also use XChecker to verify a previously configured FPGA. To verify a previously configured FPGA, connect XChecker as shown in the “XChecker Cable Connections for Verification Only” figure.
Figure 4.6 XChecker Cable Connections for Verification Only | |
Connect the XChecker RT and RD pins to the FPGA RTRIG and RDATA pins, respectively. If you used the symbols MD0 and MD1, consult the device pinout tables in The Programmable Logic Data Book for the exact locations of M0 and M1. If you used IPAD/OPAD primitives, consult The Programmable Logic Data Book for IPAD and OPAD listings or the I/O Pin Assignments Report available from the Design Manager's Report Browser.
In synchronous mode debugging, you can control the target FPGA clock through the XChecker cable. You can control the number of clock pulses applied and the frequency at which the clock cycles occur. For synchronous debugging, connect the TRIG, RT, RD, CLKO and, optionally, CLKI pins of the XChecker cable to the target FPGA, as shown in the “XChecker Operation Mode Connections” table and the “Cable Connections and Definitions” table. Also, refer to the “XChecker Cable Connections for Synchronous Debugging” figure for connection information. This XChecker cable configuration allows you to download, verify, and debug your design in the synchronous mode.
Figure 4.7 XChecker Cable Connections for Synchronous Debugging | |
To allow the XChecker clock to control the target FPGA system clock, connect XChecker's CLKO pin to the pin that you assigned as the FPGA's clock pin. All the synchronous logic should be connected to this clock source to do synchronous debugging.
The source of the CLKO clock signal can come either from an internally generated XChecker clock oscillator or from an external clock oscillator that you provide.
Settings CLKO Clock Source command from the Hardware Debugger menus and select the Use XChecker Clock setting from CLKO Clock Settings dialog box. Settings CLKO Clock Source command and select the Use CLKI setting from CLKO Clock Settings dialog box. To use an external trigger, such as the terminal count of a counter or some other condition in your target board to initiate a readback, connect the external trigger signal to the XChecker TRIG pin. TRIG is active-High.
You do not need the TRIG signal if you plan to use an internal trigger, such as the Enter key on the keyboard to initiate a readback.
Connect the XChecker RT and RD pins to the FPGA RTRIG and RDATA pins, respectively. If you used the symbols MD0 and MD1, consult the device pinout tables in The Programmable Logic Data Book for the exact locations of M0 and M1. If you used IPAD/OPAD primitives, consult the I/O Pin Assignments Report available from the Design Manager's Report Browser.
This configuration allows the target system to run while a readback is executed. You do not need to provide the system clock to XChecker, because readback is executed independently of the system clock. Connect the system clock so that it controls the device flip-flops directly. Thus, the CLKI and CLKO pins on the XChecker cable are not used for asynchronous debugging.
Connect the external trigger and the RD and RT pins as explained in the previous “Connecting for Synchronous Debugging” section. Also, refer to the “XChecker Cable Connections for Asynchronous Debugging” figure for connection information.
Figure 4.8 XChecker Cable Connections for Asynchronous Debugging | |
