Verifying Design Logic

The Verify Bitstream command verifies a design that you downloaded using a BIT file. To verify or debug a device, meet the following criteria.

• Use a BIT file as input.
  
  
• Generate a logic allocation (design_name.ll) file in the design directory by doing one of the following.
  
  
  • Use the -l option in BitGen.
    
    
  • Enable the readback option as specified in the “Design Preparation” chapter.
    
    
• If you have an XC4000 or XC5200 design, do the following.
  
  
  • Set the readback clock to CClk.
    
    
  • Include the READBACK symbol in your design.
    
    
  • Include the STARTUP symbol with an inverter on the RESET pin if you plan to reset your design using the Pulse /RESET button located on the Debug Control Panel.
    
    
• Use the XChecker cable.
  
  The XChecker must be configured for verification or debugging. Refer to the “XChecker Operation Mode Connections” table and the “Cable Connections and Definitions” table in the “Connecting Your Cable” chapter for information.
  
  

During verification, the XChecker cable reads the configuration data from the connected FPGA and verifies that it is the same as the downloaded configuration data.

1. Select Download Verify Bitstream or click the following toolbar button.
   
   
   
   The device's configuration is read back and compared to the downloaded data to ensure that the device was properly configured.
   
   
2. When verification is completed, a message lets you know whether verification succeeded or failed. If verification failed, the message also informs you of the number of mismatched bits.