This section describes the components on the FPGA Demonstration Board which are used with the XC4003E device. The following schematic shows this device.
Figure 1.6 XC4003E Schematic |  |
The XC4003E FPGA occupies socket U5 on the demonstration board.
All pins of the XC4003E connect to the headers that surround the FPGA socket. These pins provide convenient points for probing signals or making wirewrap connections to other circuitry, including the prototype area. Pin numbering increases from the inside row to the outside, counterclockwise. See the corners of each header for the starting number of that header.
The following sections describe each of the SW2 switches. For more information on configuring the XC40003E device, see the “Mode Switch Settings” section.
This switch turns the unregulated power input on or off to the +5 V regulator U3.
With MPE turned on and SPE turned off, the configuration PROM (U2) is reset by the RESET pushbutton (SW4). Configuration mode must be set to master-serial. After a Reset or powerup, the first bitstream stored in the serial PROM is loaded into the XC4003E. Pressing RESET resets the serial PROM address pointer. Pressing PROG (SW6) loads the XC4003E with the first bitstream again. If you press PROG without pressing RESET, the XC4003E is loaded with the next bitstream that is stored in the serial PROM. The size of the serial PROM limits the number of bitstreams that can be sequentially loaded.
With SPE turned on and MPE turned off, the configuration PROM (U2) is reset by the XC4003E's INIT output, which is driven Low whenever you press PROG (SW6). The first bitstream stored in the serial PROM is loaded into the XC4003E.
MPE and SPE must not be on at the same time, one must be off when the other is on. MPE and SPE are only used in conjunction with the serial PROMs. The serial PROMs must be configured as OE/!Reset to allow MPE and SPE to function properly.
These three switches must be on to configure the XC4003E using the XChecker/Parallel Cable III. When these switches are on, the FPGA is in slave serial mode. To configure the XC4003E from the onboard serial PROM, these three switches must be off. This places the FPGA in master serial mode.
When this switch is on, it connects the RESET pushbutton (SW4) to XC4003E pin 56.
When this switch is on, it connects the XC3020A INIT pin to the XC4003E INIT pin. This connection is used to configure FPGAs in a daisy chain with the XC4003E at the head of the chain.
INIT should only be used to configure FPGAs in a daisy chain.
The following table provides a detailed description of the J2 XChecker/Parallel Cable III connector.
| Pin | Name | Function | Pin | Name | Function |
| J2-1a | VCC | Supplies +5 V to the cable. | J2-2 | RT | Read Trigger allows XChecker cable to trigger a readback of the XC4003E. Connects to XC4003E pin 32. |
| J2-3a | GND | Supplies ground reference to the cable. | J2-4 | RD | Used by XChecker cable for readback data. Connects to XC4003E pin 30. |
| J2-5 | N.C.b | J2-6 | TRIG | XChecker cable input that allows an external event to trigger readback of the XC4003E or output a burst of clocks to the XC4003E. Connects to tiepoint J10-1. | |
| J2-7a | CCLK | Provides the clock during configuration or readback. Connects to XC4003E input pin 73. | J2-8 | N.C.b | |
| J2-9a | DONE | Indicates when configuration is complete. Connects to XC4003E output pin 53. | J2-10 | TDI | Inputs boundary-scan data to the XC4003E. Connects to XC4003E pin 15. |
| J2-11a | DIN | Provides configuration data during configuration. Connects to XC4003E DIN input pin 71. | J2-12 | TCK | Input boundary scan clock to the XC4003E. Connects to pin 16. |
| J2-13a | PROG | Provides program pulse causing the FPGA to configure. Connects to XC4003E PROG input pin 55. | J2-14 | TMS | Boundary scan mode input to the XC4003E. Connects to pin 17. |
| J2-15 | INIT | Goes Low if CRC error occurs during configuration. Connects to XC4003E INIT pin 41. | J2-16 | CLK1 | A system clock input to XChecker cable to be controlled and output on CLK0. Connects to tiepoint J10-2. |
| J2-17 | RST | Connects to jumper J7. If connected, allows XChecker cable to provide a Reset input (same as pressing the Reset button). | J2-18 | CLK0 | A system clock output controlled by XChecker cable. Used to single-step or burst clocks to the XC4003E. Connects to tiepoint J10-3. |
| a Denotes pins supported by the Parallel Cable III b No pin connection | |||||
The D/P wire from the FPGA header on the Parallel Cable III is connected to J2-9 DONE pin.
Jumper J7 allows the XChecker signal RST on J2-17 to drive the reset line on the demonstration board. Tiepoint pins jumper the following XChecker signals into the circuit. Tiepoint J10-1 connects to TRIG on J2-6; Tiepoint J10-2 connects to CLK1 on J2-16; and, Tiepoint J10-3 connects to CLK0 on J2-18. See the “XChecker/Parallel Cable III Connector (J2)” table for more details on the cable and pin connections.
This serial PROM configures the XC4003E or the XC4003E and XC3020A connected in a daisy chain. The configuration mode must be in the master serial mode to configure from the serial PROM.
