This section describes the components on the FPGA Demonstration Board which are for the XC3020A device. The following figure is a schematic of the FPGA Demonstration Board utilizing this device.
Figure 1.7 XC3020A Schematic |  |
The XC3020A FPGA occupies socket U4 on the demonstration board.
All pins of the XC3020A FPGA connect to the headers that surround the FPGA socket. These pins provide convenient points for probing signals or making wirewrap connections to other circuitry, such as the prototype area. Pin numbering increases from the inside row to the outside, counterclockwise. See the corners of each header for the starting number of that header. Refer to the “I/O Line Connections for XC3020A and XC4003E Devices” table for information.
The XC3020A I/O pins 2 through 9 and 61 through 68 connect to XC4003E pins 3 through 10 and 77 through 84, respectively. The XC3020A pins share the XC4003E probe points header.
The following sections describe each of the SW1 switches. For more information on configuring the XC3020A device, see the “Mode Switch Settings” section.
INP is an extra switch, which you can connect to provide an extra logic input to the XC3020A pin 46 and the XC4003E pin 69. The FPGA input pins are set to a logic "1" when the switch is on and a logic "0" when the switch is off.
The FPGA pins connected to this switch are intended for use as inputs. However, the pins have a 1 kilohm resistor that isolates them from the switch. Therefore, the pins can be defined as outputs. It is also possible to drive the pins from an external source by connecting the source signal to the FPGA probe point header. See the following figure for details.
Figure 1.8 Configuration Switch SW1 | |
When MPE is on and SPE is off, the configuration PROM (U1) is reset by the RESET pushbutton (SW4). Configuration must be set to the master serial mode. After a Reset or powerup, the first bitstream stored in the serial PROM is loaded into the XC3020A FPGA. IF you press RESET, the serial PROM address pointer is reset. If you press PROG (SW6), the XC3020A is loaded with the first bitstream again. If you press PROG, and do not press RESET, the XC3020A is loaded with the next bitstream stored in the serial PROM. The number of bitstreams that can be sequentially loaded is limited by the size of the serial PROM.
When SPE is on and MPE is off, the configuration PROM (U1) is reset by the XC3020A's INIT output, which is driven Low whenever you press PROG (SW6). The first bitstream stored in the serial PROM is loaded into the XC3020A FPGA.
MPE and SPE must not be on at the same time. MPE and SPE are only used in conjunction with the serial PROMs. The serial PROMs must be configured as OE/!RESET to allow MPE and SPE to function properly.
To configure the XC3020A using the XChecker/Parallel Cable III these switches must be on. This places the FPGA in slave serial mode. To configure from the onboard serial PROM, these switches must be off. This places the FPGA in master serial mode.
When this switch is on, it connects the XC4003E configuration clock (pin 73) to the configuration clock on the XC3020A (pin 60). This connection is used to configure FPGAs in a daisy chain with the XC4003E at the head.
When this switch is on, it connects the XC4003E data out line (pin 72) to the data in line of the XC3020A. This connection configures FPGAs in a daisy chain with the XC4003E at the head.
MCLK and DOUT should only be used to configure the FPGAs in a daisy chain.
The following table describes the pins and functions of the XChecker/Parallel Cable III J1 connector.
| Pin | Name | Function | Pin | Name | Function |
| J1-1a | VCC | Supplies +5 V to the XChecker cable. | J1-2 | RT | Allows XChecker cable to trigger a readback of the XC3020A. Connects to XC3020A pin 26. |
| J1-3a | GND | Supplies ground reference to XChecker cable. | J1-4 | RD | Used by XChecker cable for readback data. Connects to XC3020A pin 25. |
| J1-5 | N.C.b | J1-6 | TRIG | XChecker cable input that allows an external event to trigger readback of the XC3020A or outputting a burst of clocks to the XC3020A. Connects to tiepoint J3-1. | |
| J1-7a | CCLK | Provides clock during configuration or readback. Connects to XC3020A input pin 50. | J1-8 | N.C.b | |
| J1-9a | D/P | Starts configuration and indicates completion. Connects to XC3020A DONE/PROGRAM pin 45. | J1-10 | N.C.b | |
| J1-11a | DIN | Provides configuration data during configuration. Connects to XC3020A DIN input pin 58. | J1-12 | N.C.b | |
| J1-13 | N.C.b | J1-14 | N.C.b | ||
| J1-15 | N.C.b | J1-16 | CLKI | System clock input to XChecker cable to be controlled and output on CLKO. Connects to tiepoint J3-2. | |
| J1-17 | RST | Connects to jumper J5. If connected, allows XChecker cable to provide a Reset input (same as pressing Reset button). | J1-18 | CLKO | System clock output controlled by XChecker cable; used to single-step or burst clocks to the XC3020A. Connects to tiepoint J3-3. |
| a Denotes pins supported by the Parallel Cable III. b No pin connection | |||||
Jumper J5 allows the XChecker cable signal RST on J1-17 to drive the reset line on the demonstration board. Tiepoint pins jumper the following XChecker cable signals into your circuit. Tiepoint J3-1 connects to TRIG on J1-6; Tiepoint J3-2 connects to CLK1 on J1-16; and, Tiepoint J3-3 connects to CLK0 on J1-18. See the “XChecker/Parallel Cable III Connector J1” table for more information on cable connections.
This serial PROM configures the XC3020A. You must use the master serial mode to configure from the serial PROM.
R1, C5 and R2, C6 are two RC networks that connect to the XC3020A at pins 12 and 14. These RC networks are for use in a relaxation oscillator such as the circuit is shown in the following figure.
Figure 1.9 Relaxation Oscillator Schematic | |
With the components provided, R1 = R2 = 100 kilohms and C5 = C6 = 0.1uF, the oscillator generates an output frequency of approximately 100 Hz.
The following figure shows the RC Network waveforms.
Figure 1.10 RC Network Waveforms | |
The formula for calculating the RC network is as follows.
T = T1 + T2 = N ((R1C5) + (R2C6))
where:
N = approximately 0.35 for TTl threshold
= approximately 0.75 for CMOS threshold
when the FPGA allows each capacitor to discharge during the opposite timing phase.
