This appendix describes all of the attributes that you can place into your schematic for an XC9500 or an XC9500XL design. The attributes supported are as follows:
Except where noted, attributes can be applied to either component instances or their output nets.
Input buffers (IBUF)
Maps the tagged input buffers to a global net.
BUFG=CLK applied to an IBUF is equivalent to using a BUFG symbol. BUFG=OE applied to an IBUF is equivalent to using a BUFGTS symbol. BUFG=SR applied to an IBUF is equivalent to using a BUFGSR symbol.
BUFG={CLK | OE | SR }
where CLK, OE, and SR indicate clock, output enable, or set/reset, respectively.
Attached to an IBUF instance or the input pad net connected to an IBUF input.
Assign to an IBUF instance or the input pad net connected to an IBUF input. This statement maps the signal named “clk1” to a global clock net.
NET clk1 BUFG=CLK ;
Internal combinational logic nodes.
Forces a node to be collapsed into all of its fanouts
COLLAPSE
Attached to a logic symbol or its output net.
This statement forces the logic driving net ABC to collapse into all its fanouts.
NET ABC COLLAPSE ;
The design
You can place the global PART attribute in your schematic to select the target device for your design. Refer to the Release Document for a list of device names supported by the software.
The format of the PART value is as follows:
PART=dddd-ss-pppp
dddd is the device number with optional “XC” prefix, for example 95108 or XC95108, 9536XL or XC9536XL
ss is the speed grade, for example 10
pppp is the package type and pin count, for example PC84
You must specify a complete part value in the PART attribute; you may not use wildcard symbols (*).
Instantiate a CONFIG symbol and attach the PART attribute to it.
Clock nets.
A convenient way of defining a clock period for registers attached to a particular clock net
PERIOD=period [units]
where
period is the required clock period
units is an optional field to indicate the units for the clock period. The default is nanoseconds, but the timing number can be followed by ps, ns, us, or ms to indicate the intended units.
Attached to a clock input pad net.
PERIOD=40
This statement assigns a clock period of 40 ns to the input pad net named ABC.
NET ABC PERIOD=40 ;
Period timing constraints can be entered in the global tab for each input pad signal used as a clock.
Custom behavioral module symbols.
The FILE=file_name attribute on a custom symbol specifies the name of the file containing the logical definition for that symbol when the logic is expressed in behavioral form instead of an underlying schematic. If the logic for your custom symbol is defined by an underlying schematic (i.e., a user macro), you do not need a FILE attribute.
Specify filename either with or without extension. The software will search for acceptable netlist or equation (Plusasm) files. Specify the directory path if necessary.
FILE=[path]filename[.extension]
Where extension is one of .edn, .edf, .edif, .sedif, .xnd, and .pld.
Attach to a custom behavioral module symbol.
I/O pads or internal logic components.
Use the LOC=pin_name attribute on a PAD symbol or the connected pad net to assign the signal to a specific device pin. The PAD symbols are IPAD, OPAD, IOPAD, and UPAD.
Use the LOC=FBnn [_mm] attribute on any internal logic symbol, its output net, any output or I/O pad symbol or its connected pad net to assign the logic function to a specific function block or macrocell in the target device.
The pin name is Pnn for PC, PQ or VQ packages; the nn is a pin number. The pin name is rc (row, column) for BG or PG packages. Examples are LOC=P24 and LOC=G2. For function block assignment, use LOC=FBnn on an internal logic component or its output net. To assign a logic element to a specific macrocell, use LOC=FBnn_mm.
LOC=Pnn
LOC=rc
LOC=FBnn
LOC=FBnn_mm
Pin assignment using the LOC attribute is not supported for bus pads such as OPAD8.
Attach LOC=Pnn|rc to a pad symbol or attached pad net. Attach LOC=FBnn[_mm] to an internal symbol, its output net, an output pad symbol or its attached pad net.
NET ABC LOC=P12;
Location constraints for input and output pad signals can be entered in the Ports tab.
Unused device pins.
PROHIBIT allows you to reserve device pins for later use, or simply to prevent them from being used at all. For instance, if you anticipate design changes in the future and want to set traces on your printed circuit board now, you can use PROHIBIT to prevent the fitter from using pins associated with those traces. Then, when you decide to use the traces, you can use the LOC attribute to assign those pins to new input/output buffers you place in your design.
The pin name is Pnn for PC, PQ or VQ packages; the nn is a pin number. The pin name is rc (row, column) for BG or PG packages. The PROHIBIT attribute can also accept a comma-separated list of pin names. Examples are PROHIBIT=P24 and PROHIBIT=G2.
PROHIBIT=Pnn[Pnn]...
The syntax PROHIBIT=Pnn:Pmm will not work since CPLD has pin names like PA20. This prevents range definition.
Instantiate a CONFIG symbol and attach the PROHIBIT attribute to it.
PROHIBIT=P12,P13,P14;
PROHIBIT constraints can be entered using a dialog box provided in the Ports tab.
Internal logic components.
By default, all macrocells operate in the standard power mode, providing the fastest possible speed. You can change the default to low-power using the Design Manager option. To set the power mode on a specific logic function in your design, apply the PWR_MODE attribute to the symbol or its output net.
PWR_MODE=LOW|STD
Attached to an internal symbol or its output net.
INST ABC PWR_MODE=LOW;
Internal combinational nodes.
Use the logic optimization attributes to control collapsing at specific points in your design. Logic optimization attributes are normally not required to process designs.
The KEEP attribute inhibits collapsing of a logic function into any of its fanouts.
KEEP
Attach to an internal symbol or its output net.
NET ABC KEEP;
Registers and registered macros.
The INIT attribute specifies the initialization value to be preloaded into a register upon power-up. INIT=R specifies a preload value of 0 (Reset) and INIT=S specifies a preload value of 1 (Set). This attribute can be applied to flip-flops or any component containing a register, or their output nets.
INIT=R|S
Attach to a flip-flop or any component containing a register, or its output net.
The following sets a preload value of 0 on element ABC..
INST ABC INIT=R;
Output and I/O pads.
The FAST attribute can be placed on an output pad or I/O pad to select the fast slew-rate operation of the CPLD output-pin driver.
The SLOW attribute selects the slew-rate limited control.
FAST
or
SLOW
Attached to an OPAD or IOPAD instance or the connected pad net.
This statement establishes a slow slew rate for an instantiation of output signal ABC.
NET ABC SLOW ;
FAST and SLOW slew-rate can be selected for any output pad signals in the Ports tab.
Internal combinational nodes.
The NOREDUCE attribute tells the fitter to disable Boolean logic minimization for the attached component. You need to use the NOREDUCE attribute if you want to specify redundant logic in a portion of your design to avoid a potential race condition. The NOREDUCE attribute also identifies the output node of a combinational feedback loop. For example, you would use NOREDUCE on the output gate when designing combinational feedback latches.
NOREDUCE
Attached to a logic symbol or its output net.
To prevent boolean reduction at node ABC:
NET ABC NOREDUCE ;
Timing paths between I/O pads and flip-flops.
The T-spec attribute definitions specify the maximum delay between groups of components. They begin with the letters “TS” and a unique identifier that can consist of letters, numbers, and the underscore character (_). The value of the T-spec attribute consists of a FROM-TO expression specifying the timing requirements between specific end points.
The full syntax is shown as follows:
TSidentifier=FROM:source_group:TO:dest_group:delay[units]
or
TSidr=PERIOD:clock_group:delay[units]
The parameters source_group and dest_group can be any of the following:
The parameter clock_group must be a TNM identifier placed on a clock input pad.
The delay parameter defines the maximum delay for the attribute, using nanoseconds as the default unit of measurement. The default units are nanoseconds, but the timing number can be followed by ps, ns, us, ms, GHz, MHz, or kHz to indicate the intended units.
Instantiate a TIMESPEC symbol and attach one or more T-spec attributes to it.
TIMESPEC TSnn=time_spec;
Clock period timing constraints can be entered in the Global tab. Input setup time and clock-to-output delay can be entered for specific pads in the Ports tab, or for all pads related to a given clock in the global tab. Combinational pad-to-pad delays can be entered in the Advanced tab, or for all pad-to-pad paths in the Global tab.
I/O pads and flip-flops.
The TNM attribute creates a timing group name for all pads or flip-flops to which it applies. These timing group names can tehn be used in timing constraints (T-specs) to define groups of timing path end-points.
TNM=group_name
Attach to pad instances, pad nets or flip-flops. Can also attach to internal nets; the software will forward-trace the TNM to all connected flip-flops or output pads.
INST FLOP1 TNM=ABC;
Timing group names can be assigned to pad and flip-flop elements in the Advanced tab.
I/O pads and flip-flops.
Timing group definitions create new timing group names based on combinations and/or filters of existing timing group names.
group_name=group1[:group2] ...
Instantiate a TIMEGRP symbol and attach one or more timing group definitions to it.
TIMEGRP group_name=...;
New timing groups can be created in the Advanced tab.
