Appendix B

CPLD Library Selection Guide

This appendix contains two tables listing CPLD components and LogiBLOX modules respectively.

Figure B.1 CPLD Schematic Components

Table B_1 CPLD Components

Component Name	Description/Features
Buffers and Inverters
BUF*, BUF4, BUF8, BUF16	Non-inverting buffer
BUFE*, BUFE4, BUFE8, BUFE16	Internal tristate buffer with active-high enable. Not available on XC9500XL devices.
BUFG*	Global clock input buffer
BUFGSR*	Global asynchronous set/reset input buffer
BUFGTS*	Global tristate control input buffer
BUFT*, BUFT4, BUFT8, BUFT16	Internal tristate buffer with active-low enable. Not available on XC9500XL devices.
INV*, INV4, INV8, INV16	Inverter
Flip-Flops
FD, FD4, FD8, FD16	D flip-flop
FDC	D flip-flop with async. clear
FDCE*, FD4CE, FD8CE, FD16CE	D flip-flop with clock enable, async. clear
FDCP*	D flip-flop with async. preset, async. clear
FDCPE	D flip-flop with clock enable, async. preset and clear
FDP	D flip-flop with async. preset
FDPE*	D flip-flop with clock enable, async. preset
FDR	D flip-flop with sync. reset
FDRE, FD4RE, FD8RE, FD16RE	D flip-flop with clock enable, sync. reset
FDRS	D flip-flop with sync. reset, sync. set
FDRSE	D flip-flop with clock enable, sync. reset and set
FDS	D flip-flop with sync. set
FDSE	D flip-flop with clock enable, sync. set
FDSR	D flip-flop with sync. set and reset
FDSRE	D flip-flop with clock enable, sync. set and reset
FJKC	J-K flip-flop with async. clear
FJKCE	J-K flip-flop with clock enable, async. clear
FJKCP	J-K flip-flop with async. clear and preset
FJKCPE	J-K flip-flop with clock enable, async. clear and preset
FJKP	J-K flip-flop with async. preset
FJKPE	J-K flip-flop with clock enable, async. preset
FJKRSE	J-K flip-flop with clock enable, sync. reset and set
FJKSRE	J-K flip-flop with clock enable, sync. set and reset
FTC	Toggle flip-flop with async. clear
FTCE	Toggle flip-flop with clock enable, async. clear
FTCLE	Loadable toggle flip-flop with clock enable, async. clear
FTCP*	Toggle flip-flop with async. clear and preset
FTCPE	Toggle flip-flop with clock enable, async. clear and preset
FTCPLE	Loadable toggle flip-flop w/ clock enable, async. clear & preset
FTP	Toggle flip-flop with async. preset
FTPE	Toggle flip-flop with clock enable, async. preset
FTPLE	Loadable toggle flip-flop with clock enable, async. preset
FTRSE	Toggle flip-flop with clock enable, sync. reset and set
FTRSLE	Loadable toggle flip-flop with clock enable, sync. reset and set
FTSRE	Toggle flip-flop with clock enable, sync. set and reset
FTSRLE	Loadable toggle flip-flop with clock enable, sync. set and reset
X74_174	6-bit data register with asynchronous clear
X74_273	8-bit data register with asynchronous clear
X74_377	8-bit data register with clock enable
Latches
LD, LD4, LD8, LD16	Transparent data latch
Shifters
BRLSHFT4	4-bit barrel shifter
BRLSHFT8	8-bit barrel shifter
SR4CE, SR8CE, SR16CE	Shift register with clock enable, async. clear
SR4CLE, SR8CLE, SR16CLE	Loadable shift register with clock enable, async. clear
SR4CLED, SR8CLED, SR16CLED	Loadable left/right shift register with clock enable, async. clear
SR4RE, SR8RE, SR16RE	Shift register with clock enable, sync. reset
SR4RLE, SR8RLE, SR16RLE	Loadable shift register with clock enable, sync. reset
SR4RLED, SR8RLED, SR16RLED	Loadable left/right shift register with clock enable, sync. reset
X74_164	8-bit serial-in parallel-out shift register with async. clear
X74_165S	8-bit loadable serial/parallel-in parallel-out shift register with clock enable
X74_194	4-bit loadable left/right serial/parallel-in parallel-out shift register
X74_195	4-bit loadable serial/parallel-in parallel-out shift register
Counters
CB2CE, CB4CE, CB8CE, CB16CE	Cascadable binary counter with clock enable, async. clear
CB2CLE, CB4CLE, CB8CLE, CB16CLE	Laudable cascabel binary counter with clock enable, async. clear
CB2CLED, CB4CLED, CB8CLED, CB16CLED	Loadable up/down binary counter with clock enable, async. clear
CB2RE, CB4RE, CB8RE, CB16RE	Cascadable binary counter with clock enable, sync. reset
CB2RLE, CB4RLE, CB8RLE, CB16RLE	Loadable cascadable binary counter with clock enable, sync. reset
CB2X1, CB4X1, CB8X1, CB16X1	Loadable cascadable up/down binary counter with async. clear
CB2X2, CB4X2, CB8X2, CB16X2	Loadable cascadable up/down binary counter with sync. reset
CD4CE	4-bit cascadable BCD counter with clock enable, async. clear
CD4CLE	4-bit loadable cascadable BCD counter with clock enable, async. clear
CD4RE	4-bit cascadable BCD counter with clock enable, sync. reset
CD4RLE	4-bit loadable cascadable BCD counter with clock enable, sync. reset
CJ4CE, CJ5CE, CJ8CE	Johnson counter with clock enable, async. clear
CJ4RE, CJ5RE, CJ8RE	Johnson counter with clock enable, sync. reset
CR8CE, CR16CE	Negative-edge binary ripple counter with clock enable, async. clear
X74_160	4-bit loadable cascadable BCD counter with parallel/trickle enables, async. clear
X74_161	4-bit loadable cascadable binary counter with parallel/trickle enables, async. clear
X74_162	4-bit loadable cascadable BCD counter with parallel/trickle enables, sync. reset
X74_163	4-bit loadable cascadable binary counter with parallel/trickle enables, sync. reset
X74_168	4-bit loadable cascadable up/down BCD counter with parallel/trickle enables
X74_390	4-bit BCD/bi-quinary ripple counter with negative-edge clocks, async. clear
Multiplexers
M2_1	2-to-1 multiplexer
M2_1B1	2-to-1 multiplexer with D0 inverted
M2_1B2	2-to-1 multiplexer with D0 and D1 inverted
M2_1E	2-to-1 multiplexer with enable
M4_1E	4-to-1 multiplexer with enable
M8_1E	8-to-1 multiplexer with enable
M16_1E	16-to-1 multiplexer with enable
X74_150	16-to-1 inverting multiplexer with enable
X74_151	8-to-1 multiplexer with enable and complementary outputs
X74_152	8-to-1 inverting multiplexer
X74_153	Dual 4-to-1 multiplexer with enables
X74_157	Quad 2-to-1 multiplexer with enable
X74_158	Quad 2-to-1 inverting multiplexer with enable
X74_298	Quad 2-input multiplexers with storage, negative-edge clock
X74_352	Dual 4-to-1 inverting multiplexer with enables
Decoders
D2_4E	2- to 4-line decoder/demultiplexer with enable
D3_8E	3- to 8-line decoder/demultiplexer with enable
D4_16E	4- to 16-line decoder/demultiplexer with enable
X74_42	4- to 10-line active-low BCD-to-decimal decoder
X74_138	3- to 8-line active-low decoder/demultiplexer with enables
X74_139	2- to 4-line active-low decoder/demultiplexer with enable
X74_154	4- to 16-line active-low decoder/demultiplexer with enables
Encoders
X74_147	10- to 4-line active-low priority encoder
X74_148	8- to 3-line cascadable active-low priority encoder
Comparators
COMP2, COMP4, COMP8, COMP16	Identity comparator
COMPM2, COMPM4, COMPM8, COMPM16	Magnitude comparator
X74_L85	4-bit expandable magnitude comparator
X74_518	8-bit identity comparator with enable
X74_521	8-bit active-low identity comparator with enable
Arithmetic Functions
ACC1, ACC4, ACC8, ACC16	Loadable add/subtract accumulator
ADD1, ADD4, ADD8, ADD16	Adder
ADSU1, ADSU4, ADSU8, ADSU16	Adder/subtracter
X74_280	9-bit odd/even parity checker/generator
X74_283	4-bit full adder with carry-in and carry-out
Input/Output Functions
IBUF*, IBUF4, IBUF8, IBUF16	Input buffer
IOPAD*, IOPAD4, IOPAD8, IOPAD16	Input/output pad
IPAD*, IPAD4, IPAD8, IPAD16	Input pad
OBUF*, OBUF4, OBUF8, OBUF16	Output buffer
OBUFE*, OBUFE4, OBUFE8, OBUFE16	Tristate output buffer with active-high enable
OBUFT*, OBUFT4, OBUFT8, OBUFT16	Tristate output buffer with active-low enable
OPAD*, OPAD4, OPAD8, OPAD16	Output pad
Miscellaneous
GND*	Ground-connection signal tag
VCC*	VCC-connection signal tag
TIMEGRP*	Timing specification group table
TIMESPEC*	Timing requirement specification table
CONFIG*	Used to carry PART and PROHIBIT attributes

* Primitive symbols (all others are macros)

Table B_2 LogiBLOX Modules

Module	Description
ACCUMULATOR	Adds data to or subtracts it from the current value stored in the accumulator register.
ADDER/SUBTRACTER	Adds or subtracts two data inputs and a Carry input.
CLOCK DIVIDER	Generates a clock pulse whose period is a multiple of the clock input period.
COMPARATOR	Compares the magnitude or equality of two values.
CONSTANT	Forces a constant value onto a bus.
COUNTER	Generates a sequence of count values.
DATA REGISTER	Captures the input data on active Clock transitions.
DECODER	Routes input data to 1-of-n lines on the output port
INPUT/OUTPUT	Connects internal and external pin signals
MULTIPLEXER	Type 1, Type 2 - Routes input data on 1-of-n lines to the output port.
PAD	Simulates an input/output pad.
SHIFT REGISTER	Shifts the input data to the left or right.
SIMPLE GATES	Type 1, Type 2, Type 3 - Implements the AND, INVERT, NAND, NOR, OR, XNOR, and XOR logic functions.
TRISTATE BUFFER	Creates a tri-stated internal data bus. Not available on XC9500XL devices.