Appendix C

Fitter Command and Option Summary

This appendix describes how to invoke the CPLD fitter, and the commands used to prepare functional and timing simulation models. All of the available fitter options are described. This chapter contains the following sections:

• “Design Manager” section
  
  
• “CPLD Command” section
  
  

Design Manager

The Design Manager invokes the Flow Engine (fitter) and option templates to control the fitting of your design.

Invoking the Fitter

1. From the Design Manager select the schematic file you want to process.
   
   File Open Project
   
   Select a file from the template's list or use the Browse key to search your directories for the file you want to process. If the file is listed on the template, highlight the file and click once on Open.
   
   
2. Select the target device. If your schematic contains a PART attribute, the specified part will appear in the Implement dialog box. You can override any of the fields in the Part Selector dialog. Otherwise, select either XC9500 or XC9500XL as the family. By default, package and speed will be automatically selected by the fitter. You can select a specific device, package or speed in an;y of the fields.
   
   
3. Open the Constraints Editor to enter timing and pad location constraints (optional). Select:
   
   Utilities Constraints Editor
   
   
4. Select options for design implementation. Select:
   
   Design Implement
   
   
5. The Design Implementation Option menu appears. Select either the Optimize Speed (default) or Optimize Density template.
   
   
6. To adjust specific fitter options, select Edit Template. Then select from the tabs all the options you want to use and press OK. See Fitter Command Parameters later in this chapter.
   
   
7. To run the fitter, click once on the run key found in the Flow Engine.
   
   

Fitter Options

This section describes fitter parameters that can be entered from the Design Manager or when using the command line on a workstation.

The Implementation Options menu contains five tabs of options for the fitter. The following summarizes fitter options:

• Basic Default Output Slew Rate - sets default output slew-rate to FAST or SLOW (default is FAST).
  
  
• Basic Macrocell Power Setting - Sets default power mode for all macrocells in the design to standard or low-power (default is Std power).
  
  
• Basic Create Programmable Ground Pins - creates additional ground pins on unused I/Os (default is OFF).
  
  
• Basic Use Design Location Constraints - if this is not checked, the program temporarily ignores all LOC attributes in the design, allowing the fitter to assign the locations of all I/O pins (default is ON).
  
  
• Basic Use Timing Constraints - turn this selection off if you want to temporarily ignore all timing specification attributes in the design (default is ON).
  
  
• Basic Use Global Clock(s) - Select this option to automatically use global clocks (GCK) for ordinary input signals used as clocks. The global clock may allow you to meet your timing constraints more easily. By default, this option is ON.
  
  
• Basic Use Global Output Enable(s) - Select this option to automatically use global output enable (GTS) for ordinary input signals used as output enable constraints. Global output enable may allow you to meet your timing constraints more easily. By default, this option is ON.
  
  
• Basic Use Global Set/Reset - Select this option to automatically use global set/reset (GSR) for ordinary input signals used as asynchronous clear or preset. By default, this option is ON.
  
  
• Advanced Collapsing Input Limit - The maximum number of function block inputs allowed as a result of logic collapsing. Default is 36.
  
  
• Advanced Collapsing Pterm Limit - The maximum number of product terms allowed as a result of collapsing (default=20 on Optimize Speed template; 90 on Optimize Density template).
  
  
• Advanced Use Multilevel Logic Optimization - Spends additional time transforming the logic in your design to new logical structures that achieve better performance and density (default=ON).
  
  
• Advanced Use Timing Optimization - enables the global timing optimization performed by the fitter; if this option is not selected, only paths with T-specs specified in the design are optimized to improve timing (default is ON in Optimize Speed template, OFF in Optimize Density template).
  
  
• Advanced Enable D to T-Type Transform Optimization - if this box is checked (default), the fitter transforms between D-type and T-type registers.
  
  
• Advanced Use Advanced Fitting - Select this option to enable an advanced fitting strategy that favors placing signals with common inputs in the same function block. This usually allows you to pack more logic into the same device. Disable this option if the software has trouble fitting a design that used to fit with an older version of software (by default, this option is ON).
  
  
• Advanced Use Local Macrocell Feedback - enables the software to use local feedback in XC9500 devices (except XC9536) whenever possible. The local feedback path takes less time than the global feedback path. Using local feedback can speed up your design but can make it difficult to keep the same timing after a design change (default is OFF).
  
  
• Advanced Use Local Pin Feedback - enables the software to use local I/O pin feedback in XC9500 devices whenever possible. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have 3-state control or slow slew rate (by default, this option is OFF).
  
  
• Interface Macro Search Path - Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with FILE-filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path. To specify multiple search paths, type in each directory name separated by a colon (:). A semicolon is automatically appended when you use the Browse button to select multiple search paths.
  
  
• Interface Rules File - Use this option only to specify a custom rule file used for translating netlist formats not normally supported by the software.
  
  
• Interface Create I/O Pads from Ports - Creates I/O pads from ports. Select this option only if your netlist does not contain either PAD symbols or top-level ports defining external signals (you do not normally need to use this option). By default, this option is OFF.
  
  
• Timing Reports Produce Post Layout Timing Report - generates static timing report.
  
  
• Timing Reports Timing Report Format - Select Summary to generate a report that contains summary information and design statistics. Select Detailed to generate a report that lists delay information for all nets and paths.
  
  
• Programming Signature/User Code - Enter a unique text string in this field to identify the signature data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the JTAG Programmer to identify the configuration data signature (usercode) of a programmed XC9500 device.
  
  
• Programming Jedec Test Vector File - Use this option to select a test vector file (.tmv) produced by the XABEL compiler to incorporate into the JEDEC programming file to a perform functional test (INTEST).
  
  

CPLD Command

The cpld command invokes the CPLD design implementation software (the fitter). The command is run in a UNIX command window and is only supported on UNIX workstations. Your current working directory must be set to the project directory which contains your design source netlist files before invoking cpld.

Invoking the Fitter

The format of the cpld command is:

cpld [options] design_name

Invoking the cpld command with no parameters produces a listing of all available command-line options.

The design_name is the name of the top-level design netlist file, without path qualifiers, and either with or without extension.

Schematics must first be translated into either an EDIF-formatted netlist (design_name.edif). XNF formatted netlists are also acceptable from tools that do not have EDIF, but EDIF is preferred. We strongly recommend that you generate new EDIF netlists from existing schematics rather than trying to reuse existing XNF netlists. Also, your netlists must be created using schematic capture libraries provided by Xilinx or your CAE tool vendor for use with the current version of Xilinx software.

If design_name is specified without extension, the cpld command searches for source files in the following order:

1. Synopsys Design Compiler or FPGA Compiler netlist (design_name.sxnf)
   
   
2. Xilinx PLUSASM equation file (design_name.pld)
   
   
3. XNF netlist (design_name.xnf)
   
   
4. Synopsys Design/FPGA Compiler EDIF netlist (design_name.sedif)
   
   
5. EDIF netlist (design_name.edn, design_name.edf or design_name.edif)
   
   
6. Xilinx NGO (unexpanded) database file (design_name.ngo)
   
   
7. Xilinx NGD (expanded) database file (design_name.ngd)
   
   

Fitter Options

The [options] field of the cpld command represents an optional list of one or more command-line parameters. Invoking the cpld command with just the design name and no option parameters runs the fitter with all default conditions, including automatic device selection.

The following are the cpld command-line parameters that apply to schematic design entry:

• -autoslewpwr - reduces slew rate before reducing power mode if autopwrslew is enabled.
  
  
• -autopwrslew - reduces power mode and/or slew rate if timespecs can still be met or if no timespecs apply.
  
  
• -detail - produces a detailed path timing report (design_name.tim) instead of the default summary report.
  
  
• -grounds - creates programmable ground pins on unused I/Os.
  
  
• -ignoreloc - temporarily ignores all LOC attributes in the schematic, allowing the fitter to assign the locations of all I/O pins.
  
  
• -ignorets - temporarily ignores all timing specification attributes in the schematic.
  
  
• -inputs <n> - maximum number of function block inputs allowed as a result of logic collapsing. Default is 36.
  
  
• -localfbk - uses local feedback. Enables the software to use local feedback whenever possible. The local feedback path takes less time than the global feedback path. Using local feedback can speed up your design but can make it difficult to keep the same timing after a design change. XC9500 only.
  
  
• -loweffort - low fitting effort, to save processing time.
  
  
• -lowpwr - uses the low-power mode by default for all macrocells in the design (default is normally standard power).
  
  
• -nodt - disables transformation between D-type and T-type registers.
  
  
• -nogck - disables global clock optimization.
  
  
• -nogsr - disables global set/reset optimization
  
  
• -nogts - disables global output-enable (GTS) optimization.
  
  
• -nomlopt - disables multi-level logic optimization.
  
  
• -nota - do not generate a summary static timing report.
  
  
• -notiming - inhibits the default global timing optimization performed by the fitter; only paths with T-specs specified in the schematic are optimized to improve timing.
  
  
• -notsim - disables generation of timing simulation file (.nga).
  
  
• -nouim - disables implementation of AND functions in FASTconnect. XC9500 only.
  
  
• -noxor - disables transformation of sum-of-product XOR logic into macrocell XOR gates.
  
  
• -p part_type - specifies the target device type or set of devices from which to choose (default is automatic device selection from the XC9500 family); where part_type can be:
  
  
  • 9500 = any XC9500 family device (auto selection)
    
    
  • 9500xl = any XC9500XL family device (auto selection)
    
    
  • “95ddd[xl][-ss][-pppp]” - where 95ddd is the device code (such as 95108), ss is the speed grade, pppp is the package code (such as PQ160), and an asterisk (*) can be used as a wildcard string (quotes required around part_type when asterisk is used).
    
    
• -pinfbk - uses pin feedback. Enables pin feedback whenever possible. The software uses the pin feedback path instead of the FastCONNECT path for output pin signals that do not have 3-state control or slow slew rate. XC9500 only.
  
  
• -pinlock - uses the guide file (design_name.gyd) from the last successful invocation of the fitter to reproduce the same pin locations (default is automatic pin assignment).
  
  
• -pterms nn - the maximum number of product terms allowed as a result of collapsing (default=20).
  
  
• -s signature - specifies the user signature string (up to 4 alphanumeric characters) to be programmed into the device for identification purposes (default is the design name).
  
  
• -slowslew - applies slow output slew-rate as default (default is fast).
  
  
• -ucf - reads user constraints from filename.ucf. By default, design_name.ucf is read if it exists.
  
  
• -xactfit - Use this option only if you have a design implemented in XACT v6 and cannot get the same pinout using the current software. The default is advanced fitting.