Placing and Routing Non-Timing Driven Designs

When targeting the Virtex and Spartan2 device families on designs that are run without timing constraints, you may notice lower design performance results from the Place and Route process. To get a more realistic estimate of how your design will perform without timing constraints applied, do the following.

1. In the Flow Engine, set your run target to Place&Route.
   
   See the “Setting a Run Target” section for more information.
   
   
2. Select Flow Run.
   
   
3. After the Flow Engine has finished routing your design, select Setup FPGA Re-entrant Route to open the dialog box shown in the following figure.
   
   

   Figure 3.24 FPGA Re-entrant Route Dialog Box

4. Specify the number of Clean-up Passes to run. For information on clean-up passes, see the “FPGA Re-entrant Route Dialog Box” section of the “Menu Commands” chapter.
   
   
5. Click OK.
   
   
6. Select Flow Step Back.
   
   
7. Select Flow Run.
   
   
8. Check the P&R Report and Post Layout Timing Report in the Report Browser for improved performance results. See the “Viewing Reports” section for information on viewing the report.