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This section describes all of the menu commands for the Design Manager and Flow Engine combined. The commands are presented in alphabetical order.
The File menu display up to four of the most recently used projects. To open a project, click on the appropriate file listed in the menu.
Use this command to terminate the current Flow Engine execution.
Note: To set a run target, use the Setup Stop After command.
Use this command to display program information, including the software version and serial number, and the copyright notice. A dialog box displays this information.
Use this command to display program information, including the software version and serial number, and the copyright notice. A dialog box displays this information.
Use this command to open the Advanced dialog box, shown in following figure. Set the options in this dialog box to configure the implementation flow and control aspects of the Flow Engine interface.
The following options are available in this dialog box.
Use this command to launch the Chip Viewer. This tool presents a graphical view of the final fitting report for CPLDs. You can use the Chip Viewer before or after the Fitting process.
If you run the Chip Viewer before Fitting, the viewer reads from the design netlist. Select a device to get basic design information, set I/O assignments and pin-locking, and modify the UCF file.
If you run it after Fitting, the viewer reads the fitting results in the .vm6 file. It allows you to view the final fit and all pin assignments, connections between macrocells and details about macrocell use, and power settings and slew rates.
Note: The Chip Viewer is supported for CPLD device families only.
Use this command to close the Flow Engine window. Use this command when you are finished implementing the design or no longer need the Flow Engine.
Use this command to open the Command History utility and display the commands and options that have been run in the flow for the current implementation revision. This utility is useful for reviewing the commands and options that were used while executing the flow. This utility is shown in the following figure.
The following options are available.
Use this command to open the Command Preview utility and display the commands and options that remain to be run in the flow for the current implementation revision. This utility is useful for determining which commands will be executed in the flow and whether the correct options have been set. This utility is shown in the following figure.
The following options are available.
Use this command to launch the Constraints Editor. This tool allows you to create new constraints and edit existing ones after running the Translate step in the Flow Engine.
The Constraints Editor accepts NGD and, optionally, UCF files as input and writes out a valid UCF file. You can use this valid UCF file as input to an automatic implementation of a revision or to the Translate step, if you are implementing a revision in separate steps.
For additional information, see the Constraints Editor Guide.
Use this command to make a copy of the currently selected implementation revision. The new implementation revision contains the same data as the selected implementation revision. When you use the Copy Revision command, the Copy As dialog box appears, as shown in the following figure. After the Design Manager creates the copy, it displays a new implementation revision icon in the project view.
Type a name for the implementation revision copy in the Copy As field.
Use this command to delete the currently selected project, design version, or implementation revision. Select the appropriate icon and select Design Delete or press the Delete key on your keyboard. You are prompted to confirm that you really want to delete the selected data.
Use this command to delete a project along with all its associated files in the project directory. This command opens the Delete Project dialog box, shown in the following figure. You are presented with a list of projects from which you can select a project to delete. To delete a project, select a project and click Delete.
The following options are available in this dialog box.
Use this command to close the current project and exit the Design Manager. All data is saved automatically upon exit. You are prompted to confirm that you really want to quit.
Use this command to export your design data. It opens the Export dialog box, shown in the following figure. This command is useful for transferring design data created in the Design Manager to other environments.
Note: The Flow Engine automatically exports certain files to your design directory based on the targets selected in the Options dialog box.
The following options are available in this dialog box.
Use this command to launch the Floorplanner from the Design Manager. The Floorplanner is a graphical placement tool that gives you control over placing a design into a target FPGA using a drag and drop paradigm with the mouse pointer.
The Floorplanner displays a hierarchical representation of the design in the Design window using hierarchy structure lines and colors to distinguish the different hierarchical levels. The Floorplan window displays the floorplan of the target device into which you place logic from the hierarchy.
For online help for this tool, obtain Help from within the Floorplanner.
Note: The Floorplanner is supported for all XC4000 families, Virtex, Spartan/XL, and Spartan2 FPGA device families only.
Use this command to launch the Flow Engine. You can use the Flow Engine to implement a design. You can set compile and flow options from within the Flow Engine.
For additional online help for this tool, obtain Help from within the Flow Engine.
Use this command to view the Flow Engine log file in a separate window. The log file contains all of the messages displayed for the programs run during the implementation process.
Use this command to specify the font type and font size for the text displayed in the Flow Engine message log window. This command opens a standard font dialog box in which you can make these settings.
Use this command to launch the FPGA Editor from the Design Manager. The FPGA Editor is a graphical tool that allows you to display and configure FPGAs. You can use the FPGA Editor to edit design logic, logic placement, and signal routing.
Use the FPGA editor before the Place&Route step to place and route critical components. You can also use the editor to manually finish placement and routing if the Route process does not completely route your design.
For online help for this tool, obtain Help from within the FPGA Editor.
Note: The FPGA Editor is supported for the FPGA device families only.
Use this command to run multiple place and route passes on an implementation revision. You can indicate the number of place and route passes the software should run and the number of passes you want to save. Each pass you save is added as an implementation revision in the Design Manager project view. When you use this command, the dialog box shown in the following figure appears, in which you can make these settings.
After you run the place and route passes, the FPGA Multi-Pass Place & Route Status dialog box appears. This dialog box shows the design version name and the status of your placed and routed design, as shown in the following figure.
For more information on cost tables, best passes, and on generating a nodelist file and setting up environment variables, see the Turns Engine (PAR Multi-Tasking Option) section of the Development System Reference Guide.
Note: This command is supported for the FPGA device families only. In order to accomplish the MPPR runs, the Flow Engine generates temporary (tmp) files in your working directory. If MPPR does not complete successfully, the tmp files remain in the Design Manager project view.
The following options are available in this dialog box.
Note: Cost tables are fixed from one run to the next; however, cost tables are not an ordered set. There is no correlation between a cost table's number and its relative value.
Note: The Nodelist File option is only available on UNIX workstations.
The following options are available in this dialog box.
Use this command to reroute a previously routed design. This command opens the Re-entrant Route dialog box, shown in the following figure, which allows you to set up the conditions for your re-entrant routing. You can set the number of re-entrant routing and cleanup passes and set whether to use timing constraints for the re-entrant route process.
Note: This command is supported for FPGA device families only.
The following options are available in this dialog box.
Use this command to launch the Hardware Debugger. Use the Hardware Debugger to download a design to a device, verify the downloaded configuration, and display the internal states of the programmed device.
For online help for this tool, obtain Help from within the Hardware Debugger.
Note: The Hardware Debugger is supported for FPGA device families only.
Use this command to display the opening screen of Design Manager or Flow Engine Help. From the opening screen, you can jump to step-by-step instructions and to various types of reference information.
After you open Help, you can click the Help Topics button in the Help window whenever you want to return to the opening screen of Help.
For more information about online help, see the Using Help section of the Getting Started chapter.
Use this command to start the implementation process. This command opens the Flow Engine and begins an automatic implementation on the last implementation revision. The last revision is the bottommost revision in the Design Manager project view. However, if you changed your source design for the last revision, the New Version dialog box appears. You must set options in this dialog box before implementation can take place. See the New Version Dialog Box section for information on these options.
If you want to set implementation, simulation, and configuration options before you implement your design, set them in the Options dialog box. For more information on this dialog box, see the Options Dialog Box (FPGA) or Options Dialog Box (CPLD) section.
Note: If you want to implement a revision that is not the last revision, right-click on a revision and select Re-implement. See the Re-Implementing a Design section of the Using the Design Manager and Flow Engine chapter for information.
After you implement a design, the Implement Status dialog box appears. This dialog box is shown in the following figure.
The following options are available in this dialog box.
Use this command to launch the JTAG Programmer. Use the JTAG Programmer to download your design and configure a device from the XC4000, XC5200, Virtex, Spartan/XL, or Spartan2 FPGA families or XC9500 CPLD family.
For online help for this tool, obtain Help from within the JTAG Programmer.
Use this command to perform pin locking by placing pinout information in the user constraints file (UCF). This command allows you to use pinout information with other Xilinx implementation tools. For FPGAs, pin locations and logical pad names are read from a placed NCD file. For CPLDs, this information is read from a fitted GYD file.
This command creates a UCF file if one does not exist. If one exists, the existing user constraints are maintained, but additional pin locking constraints are added to the file. All pin locking constraints created by this command are written in a PINLOCK section within the UCF file.
After the constraints are generated, you can review the Lock Pins report by clicking View Report in the status dialog box, shown in the following figure, or by using the Utilities Lock Pins Report command.
The following options are available in this dialog box.
Use this command to open the report file generated during the execution of the Design Lock Pins command. This report contains information on the constraint conflicts between the pin locking constraints in the UCF file and the design file.
Use this command to create a new project. This command opens the New Project dialog box, shown in the following figure. In this dialog box, you can specify the design file for creating your new project.
Note: To open an existing project, use the File Open Project command.
The following options are available in this dialog box.
Note: When you browse for the input design, the software automatically fills the Work Directory field with the input design directory followed by the xproj subdirectory.
Use this command to create a new implementation revision. A new implementation revision allows you to attempt a new implementation of the design using different compile options or a different target part. When you use the New Revision command, you must make settings in the dialog box shown in the following figure. After the new implementation revision is created, a new implementation revision icon is displayed in the Design Manager project view.
The following options are available in this dialog box.
Note: When naming revisions, use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only.
Use this command to create a new design version. A new design version allows you to manage changes to the input design or logic of your design. For instance, any time your netlist data or schematic changes, you must generate a new design version.
When you use the New Version command, the New Version dialog box appears, as shown in the following figure. In the New Version dialog box, enter the information necessary to define the new design version. After the new design version is created, a new design version icon is immediately added and displayed in the Design Manager project view.
The following options are available in this dialog box.
Note: When naming versions and revisions, use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only.
Use this command to open the software manuals on the Web. If you do not have Web access, you can still access the documentation, either from the copy you installed on your local hard drive or from the CD. The manuals are opened in the default Web browser. You can set your default browser using the File Preferences command.
Use this command to open an existing project. The project consists of several files but is represented in the Xilinx Project dialog box as a single file with the .xpj extension. The Open Project command opens the Open Project dialog box, as shown in the following figure. Select a project from this dialog box.
To open one of the four most recently used projects, select a project from the project name list in the Design Manager File menu.
Note: To create a new project, use the File New Project command.
The following options are available in this dialog box.
Use this command to open the dialog box shown in the following figures. This dialog box allows you to set options used in the implementation flow. Changes made in this dialog box apply to the selected implementation revision. The following dialog box appears if you are targeting an FPGA.
The following dialog box appears if you are targeting a CPLD.
Note: If you open this dialog box from the Flow Engine while a step is running, the changes are picked up when the step is done. Subsequent steps are run with the changes you made.
This dialog box allows you to set implementation, configuration, and simulation options. It also allows you to set the Place and Route Effort Level.
This dialog box allows you to set implementation and simulation options.
Use this command to open the dialog box shown in the following figure. Use this dialog box to customize program settings, such as specifying the text editor for viewing reports. The settings you make in this dialog box are applied to all projects.
Note: The text that specifies the editor and web browser is not validated and is sent directly to the operating system. Verify the text before sending it.
The following options are available in this dialog box.
Use this command to generate timing reports. You can use this command if at least Map (for FPGAs) or Fit (for CPLDs) has completed successfully. The type, title, and file name of the report depend on the state of your design when you run this command. You cannot change the file name of the report. The following table shows the report that is generated given a particular state. The timing reports are placed in the Report Browser when complete.
State | File Name | Title |
---|---|---|
Mapped (FPGA) | map_number.twr | Logic Level Timing Report #number |
Routed (FPGA) | design_name_number.twr | Post Layout Timing Report #number |
Fitted (CPLD) | design_name_number.twr | Post Fitting Timing Report #number |
Timed | design_name_number.twr | Post Layout Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD) |
Implemented | design_name_number.twr | Post Bitgen Timing Report #number (FPGA) Post Fitting Timing Report #number (CPLD) |
This command opens a dialog box in which you can set the report format. The dialog box shown in the following figure appears if you are targeting an FPGA.
The dialog box shown in the following figure appears if you are targeting a CPLD.
Note: If you step back over a state that was necessary to generate a report, the report associated with that state is removed from the Report Browser. To restore the state and the associated reports, use the Flow Step command in the Flow Engine.
Select a timing report format. The default is Report Paths Failing Timing Constraints.
Select a timing report format.
Use this command to open a standard text editor window in which to make notes for the current project. Use the File Preferences command to specify the text editor of your choice.
Use this command to launch the PROM File Formatter. Use the PROM File Formatter to format BIT files into a PROM file compatible with Xilinx and third party PROM programmers. You can also use it to concatenate multiple bitstreams into a single PROM file for daisy chain applications.
For online help for this tool, obtain Help from within the PROM File Formatter.
Note: The PROM File Formatter is supported for the FPGA device families only.
Use this command to display information about a selected project, design version, or implementation revision. This command opens a dialog box containing information that varies depending on the selected object.
All dialog boxes contain the object name and directory, and a comment field with noted options and strategies. In addition, the Project Properties dialog box contains the input design name and path. The Revision Properties dialog box contains the part type used.
The Project Properties dialog box also contains two buttons, Version List or Revision List. If you click one of these buttons, the Files List dialog box opens, as shown in the following figure. From this dialog box, you can specify files you want to copy to your version or revision directory or a specified subdirectory.
Use this command to view reports. The Report Browser command opens the Report Browser utility. This utility contains icons that represent the reports that have been generated by the Flow Engine.
The icons change appearance to indicate whether or not you have read a report. A yellow mark in the upper left corner of the report icon indicates that the report has been generated but not read. A report icon without this mark indicates that the report has been generated and read.
To read a report, double-click the report icon. The report opens in the text editor that you specified with the File Preferences command.
Use this command to start the Flow Engine. The Flow Engine processes until it completes the target process or finishes implementing the design.
Use this command to save the current project. Using this command ensures that all comments and the state of the project and design version icons are saved.
Note: The Design Manager saves frequently so that data is almost always up to date.
Use this command to bring up the Set Constraints dialog box shown in the following figure. This dialog box allows you to identify a UCF file to constrain your design. You can specify logic placement and timing requirements in the UCF file.
This dialog box contains the Copy Constraints Data From option. Select this option to copy a constraints file into the selected implementation revision. The software uses this file to implement the design.
From the drop-down list box, select a revision that contains the UCF file you want to use, or select Custom to open the Custom dialog box and select a specific file. See the following section for information on the Custom dialog box. Select None if you do not want to constrain your design based on a previous revision or custom file.
This dialog box is shown in the following figure.
In the Constraints File field, type the name of a specific file, or click Browse to open a file selection dialog box in which you can select an existing UCF file.
Use this command to open the Set Floorplan File(s) dialog box, shown in the following figure. Use this dialog box to instruct the Design Manager to use information generated by the Floorplanner as a guide for mapping. The Design Manager obtains this information from the Floorplanner MFP file. For information on how to create the MFP file, refer to the Floorplanner Guide.
Note: This command is available for the XC4000, Virtex, Spartan, and Spartan2 device families only. If you use this command, you cannot guide mapping using the Design Set Guide File(s) command Custom option.
This dialog box contains the following options.
This dialog box is shown in the following figure. It contains the following options.
Use this command to open the Set Guide File(s) dialog box, shown in the following figure, in which you can specify a guide file. A guide file is created each time you implement your design and you can reuse this data to maintain mapping, placing, and routing consistency for FPGAs and fitting consistency for CPLDs. You can guide from an implementation revision or from a custom guide file. Guiding your design can reduce the amount of time taken for implementation.
The following options are available in this dialog box.
Note: If you select a revision, it must be a placed and routed revision. If you want to guide from a mapped file, you must use the Custom option.
Note: This option is not recommended for synthesis based designs. This option is supported for the FPGA device families only.
This dialog box is shown in the following figure. It contains the following options.
Note: If you use this option, you cannot guide mapping using the Design Set Floorplan File(s) command.
Use this command to open the Set Part dialog box shown in the following figure. This command allows you to create a new implementation revision targeted for the part you choose.
Note: After the implementation revision is created, the part cannot be changed.
The following options are available in this dialog box.
Note: When naming revisions, use the characters A through Z, a through z, 0 through 9, period (.), underscore (_), or hyphen (-) only.
This dialog box is shown in the following figure. Set the following options in the Part Selector.
Use this command to show or hide the status bar.
In the Design Manager, the status bar shows the project name, the part name if an implementation revision is selected, and the name of the selected item.
In the Flow Engine, the status bar shows the target part name for the current implementation revision, the name of the user specified constraints file, and the name of the user specified guide file.
Use this command to run the next step in the processing flow. This command allows you to single-step through the implementation process.
Note: You can use the Implementation State option in the Advanced dialog box to restore an implementation state when you have stepped forward too far.
Use this command to go back one step in the processing flow. You can use this command to back up and rerun a step using different options. The data is not deleted until you overwrite it by rerunning the step.
Note: You can use the Implementation State option in the Advanced dialog box to restore an implementation state when you have stepped back too far.
Use this command to specify a target break point where the Flow Engine will stop processing. Choose a process from the Stop After dialog box, shown in the following figure. For instance, if you want to map, place, and route your design but not create a timing simulation file or device programming file, select Stop After Place&Route.
Select a target break point from the Stop After list box. When working with an FPGA the available targets are Translate, Map, Place & Route, Timing (Sim), and Configure. When working with a CPLD the available targets are Translate, Fit, Timing (Sim), and Bitstream. The selected target appears in the Stop After field.
Use this command to create or modify your implementation, simulation, and configuration option templates. Templates provide a convenient way to have several groups of option settings that you can select from when you implement a design. Implementation and simulation options are supported for FPGAs and CPLDs. Configuration options are supported for FPGAs.
The Template Manager command opens the dialog box shown in the following figure. For more information on how to use the Template Manager, see the Working with Templates section of the Using the Design Manager and Flow Engine chapter.
The following options are available in this dialog box.
Note: Configuration options are available for FPGA devices only.
This dialog box is shown in the following figure. The following options are available in this dialog box.
Note: The title of this dialog box changes based on whether you are working with implementation, simulation, or configuration options.
Note: Any options you have entered previously are saved and appear the next time you open this dialog box.
Note: It is possible to enter options in the Customize Options dialog box that can conflict with normal Flow Engine options. It is beyond the scope of this manual to explain all the possible conflicts.
Use this command to launch the Timing Analyzer. Use the Timing Analyzer after a design has been mapped, routed, or fitted. The Timing Analyzer performs a static timing analysis of a mapped or routed FPGA or fitted CPLD design. A static timing analysis is a point-to-point analysis of a design network. It does not include insertion of stimulus vectors.
The Timing Analyzer verifies that the delay along a given path or paths meets your specified timing requirements. It organizes and displays data that indicate the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths, and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the design.
The Timing Analyzer works with synchronous systems composed of flip-flops and combinatorial logic. In a synchronous design, signals must be stable long enough to allow the clocks to change so that setup and hold violations are avoided.
For online help for the this tool, obtain Help from within the Timing Analyzer.
Use this command to show or hide the toolbar.
Use this command to show or hide the toolbox.
Use this command to determine whether a change has been made that would cause a successfully run step to be rerun. If the Flow Engine determines that a process needs to be rerun, it presents a confirmation dialog box. Click Yes and the flow is reset to run the appropriate step next. See the Smart Flow Engine Change Detection table of the Introduction chapter for information on which file changes cause steps to be rerun.
Note: The Flow Engine will not automatically begin processing the appropriate step, you must select Flow Run or Flow
Step to begin the implementation process.
This cascading menu command allows you to access Xilinx web pages through a Web browser. Use the File Preferences command to set the Web browser of your choice. You must have Web access to use these commands.
Use the Support and Services command to open the Xilinx technical support page. Use this page to access the latest design information, to search across various resources, and to access online resources directly.
Use the Xilinx Home Page command to open the Xilinx home page. This page contains links to the latest Xilinx announcements, technical support, and information on the company, its products, and investor relations.