Design Manager/Flow Engine GuideChapter 3: Using the Design Manager and Flow Engine
Running Multiple Place and Route Passes
Running multiple place and route passes allows you to automatically generate multiple place and route solutions for a design. The Place and Route process offers both the ability to generate a determinate, repeatable solution by using the same starting point, or cost table, and the ability to generate a range of unique solutions by using different cost tables.
The FPGA Multi-Pass Place & Route command automates the ability to run Place and Route several times with different cost tables. It scores each place and route pass and uses the score to determine the best passes to save. Scores are based on factors such as the number of unrouted nets, the delays on nets, and conformity to your timing constraints. The passes you save appear as implementation revisions in the Design Manager project view.
On average, design speed from an arbitrary multiple pass place and route will vary plus or minus 5 to 10% from the median design speed across all cost tables. About 1/3 of the cost tables will result in speeds within 5% of the median, 1/3 in the 5 to 10% range, and 1/3 in the 10-15% range. When comparing performance from the absolute worst cost table to the absolute best, a spread of 25 to 30% is possible.
Note: Ranges are narrower for Virtex devices and higher for XC4000 devices.
Use the FPGA Multi-Pass Place & Route command in the following situations.
- You want to evaluate whether worse than expected results are due to a poor starting point or cost table.
In this case, run multiple place and route passes at any time during the design cycle by running 3 or 4 cost tables.
- You made small changes to a design at the end of the design cycle and performance falls 5 to 10% as a result of these changes.
In this case, run 5 to 10 cost tables.
If you are working on a workstation, you can use the Nodelist File option to execute the place and route process on multiple machines. This significantly reduces the run time.
Note: The FPGA Multi-Pass Place & Route command is supported for the FPGA device families only. Using the FPGA Multi-Pass Place & Route command is not recommended for every design iteration. If you need the top performing cost tables to meet design performance, your design should be modified to remove one or more logic levels.
- In the Design Manager, select Design
FPGA Multi-Pass Place & Route to open the dialog box shown in the following figure.
The options in this dialog box are described in the “FPGA Multi-Pass Place & Route Dialog Box” section of the “Menu Commands” chapter.
- In the Initial Placement Seed (Cost Table) field, specify a placement initialization value.
The placement initialization value sets the number with which to begin the place and route attempts. Each pass receives an incremental value. The value you choose corresponds to a cost table index which initializes the place and route algorithms.
- In the Place & Route Passes to Execute field, specify the number of place and route passes to attempt.
- In the Save N Best Passes field, specify the number of place and route passes to save.
The software saves the best passes based on the iteration design scores.
- If you want to change the default prefix of the pass names, enter a new name in the Prefix for Derived Revisions field. The default prefix is rev#.
- If you are working on a workstation, you can click the Nodelist File Browse button to choose a nodelist file that you generated.
This file allows you to use multiple machine (nodes) that are networked together to run the place and route passes. For more information on generating a nodelist file and setting up environment variables, see the “Turns Engine (PAR Multi-Tasking Option)” section of the Development System Reference Guide.
- In the FPGA Multi-Pass Place & Route dialog box, click Run.
The Design Manager creates implementation revisions for the number of passes you specified in the Save N Best Passes field. After the passes are complete, the dialog box shown in the following figure appears. Click View Log File to view the log file or click View Summary Report to view the summary report.
Figure 3.25 FPGA Multi-Pass Place & Route Dialog Box