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You can copy constraints, guide, and floorplan file data to an existing implementation revision. Copy this data to your implementation revision to control the implementation of your design. Specify the data you want to copy using the Design Manager. The following sections describe how to copy this data to an existing revision.
Note: The following procedures describe how to copy data to an existing implementation revision. If you want to copy data to a new design version or implementation revision, use the Copy Persistent Data option described in the Creating a New Design Version or Creating a New Implementation Revision section.
You can use a user constraints file (design_name.ucf) to control the implementation of your design. The user constraints file can contain information on where to place I/O pins and blocks of logic and timing requirements for the design.
If you want to control the implementation of your design with a user constraints file, you can specify this file in the Set Constraints File dialog box. The software tries to implement your design to meet the specified timing requirements and other constraints.
You can select a previously routed or fitted implementation revision or a guide file to use as a guide for implementation. The procedure for guiding your implementation is the same for FPGAs and CPLDs. However, the way the design is guided differs between the two.
When guiding an FPGA design, the software attempts to use the guide for placing logic and routing signals for the current implementation revision of the design. This can reduce the amount of time the software takes to place and route. Guiding a design for an FPGA works as follows.
After these components and signals are placed and routed, the remainder of the logic is placed and routed. If you have made only minor changes to your design and want the remaining logic placed and routed exactly as in your guide design, select the Match Guide Design Exactly option. This option locks the placement and routing of the matching logic so that it cannot change to accommodate additional logic.
Note: Setting the Match Guide Design Exactly option is not recommended for synthesis based designs.
For CPLDs, each time you implement your design, a guide file is created (design_name.gyd) which contains your pinout information. You can reuse this file in subsequent iterations of your design if you want to keep the same pinouts. If you select a valid implementation revision or guide file name, the pinouts from that file will be used when the design is processed.
Note: You can override guide file locations by assigning locations in your design file or constraints file.
Note: The implementation revision or revision data is based on a placed and routed design. Guide from a placed and routed file rather than a mapped file to reduce runtime. To guide from a mapped file, you must use the Custom option. If you use this option, you cannot guide mapping using the Set Floorplan File(s) command. Guided mapping is not supported for Virtex devices.
Note: For synthesis-based designs, use the Match Guide Design Exactly option only if the guide file is from the same design version.
When you use the Floorplanner, an MFP file is generated that contains mapping information. You can instruct the Design Manager to use this file as a guide for mapping an implementation revision using the Set Floorplan File(s) command. To use this command, you must select an implementation revision that has been mapped and modified using the Floorplanner. For information on using the Floorplanner, see the Floorplanner Guide.
Note: If you use the Set Floorplan File(s) command you cannot guide mapping using the Set Guide File(s) command Custom option. The Set Floorplan File(s) command is available for the XC4000, Virtex, Spartan, and Spartan2 device families only.
Note: By default, this option is enabled and instructs the software to use the specified floorplan file. If you do not want to guide your design but want to keep your floorplan file intact, disable this option.