Spartan Implementation Options

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “Spartan Translate Tab”
  
  
• “Spartan Optimize and Map Tab”
  
  
• “Spartan Place and Route Tab”
  
  
• “Spartan Timing Reports Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Spartan Translate Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.1 Spartan Translate Tab

Macro Search Path

Use this option to add the specified search path to the list of directories to search when resolving file references (that is, files specified in the schematic with FILE=filename property). This option also supplies paths for macros (design_name.nmc) or other directories containing NGO files. Specify a macro search path or click Browse to look for a path to add as a macro search path.

To specify multiple search paths, type in each directory name separated by a semicolon (;). A semicolon is automatically appended when you use the Browse button to select multiple search paths.

Rules File

Use this option to specify which executables are used to convert outside netlists to NGO netlists. Specify a rules file or click Browse to look for a file to add as a rules file.

Create I/O Pads from Ports

This option adds PAD properties to all top level port signals. Select this option if your simulation netlist format is an EDIF file in which PAD symbols were translated into ports. If you do not select this option for one of these EDIF files, the mapper reads the design incorrectly. By default, this option is off.

Note: PAD symbols are translated into ports in all Mentor Graphics and Cadence EDIF files. This option is set automatically for EDIF files from either of these vendors.

Spartan Optimize and Map Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.2 Spartan Optimize and Map Tab

Logic Optimization Options

The Logic Optimization Options group box contains the following options.

• Trim Unconnected Logic
  
  Select this option to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.
  
  
• Replicate Logic to Allow Logic Level Reduction
  
  Use this option to replicate a single driver that drives multiple loads and map it as separate components that drive individual loads. This option is useful for creating a mapping strategy that may more readily meet your timing constraints. It reduces the number of logic elements through which a signal must pass, thereby eliminating path delays. By default, this option is on.
  
  
• Generate 5-Input Functions
  
  Select this option to map each five-input logic function to a single CLB. This option can sometimes reduce the number of cell-to-cell delays at the expense of increased CLB count. By default, this option is off.
  
  

Map Options

The Map Options group box contains the following options.

• CLB Packing Strategy
  
  This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop input) pins on CLBs, and reducing minimum signal combining requirements. The default is Fit Device.
  
  

  Note: Although the CLB Packing Strategy option makes a design denser, it can also adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option if you are willing to trade performance for density.

  • Fit Device
    
    Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.
    
    
  • Off
    
    Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.
    
    
• Pack CLB Registers for
  
  This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the “Register Ordering” section of the Development System Reference Guide. The default is Structure.
  
  
  • Structure
    
    Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.
    
    
  • Minimum Area
    
    Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.
    
    
• Pack I/O Registers/Latches into IOBs for
  
  This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.
  
  
  • Inputs Only
    
    Select Inputs Only to pack flip-flops or latches into input I/O cells.
    
    
  • Outputs Only
    
    Select Outputs Only to pack flip-flops or latches into output I/O cells.
    
    
  • Inputs and Outputs
    
    Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.
    
    
  • Off
    
    Select Off to pack flip-flops or latches as specified by your design entry method.
    
    
• Use Generic Clock Buffers (BUFGs) in place of BUFGPs and BUFGSs
  
  Select this option to replace primary and secondary clock buffers with generic clock buffers before mapping occurs. This option is useful when working with design entry tools that generate only BUFGPs or BUFGSs. By default, this option is off.
  
  
• Ignore RLOC Constraints
  
  Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.
  
  

  Note: To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

• Create Detailed Map Report
  
  Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.
  
  

Spartan Place and Route Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.3 Spartan Place and Route Tab

Router Options

The Router Options group box contains the following options.

• Run _ Routing Passes
  
  Use this option to set the maximum number of routing passes that the router runs in a design. The router attempts to completely route a placement with each pass. You can set the number of passes to a value from 1 to 1000 or to Auto.
  
  Auto runs the router until specific exit conditions are met. At place and route effort levels of 3, 4, or 5, the router runs until it routes to 100% completion and meets all timing constraints or until it determines it cannot complete the routing. At levels of 1 or 2, the router stops after a predetermined number of passes. With all settings, the router exits immediately after it routes all connections and meets all timing constraints. A higher number of passes provides better routing results at the expense of longer run times. The default is Auto.
  
  
• Run _ Delay-Based Cleanup Passes
  
  Use this option to further optimize routing of an already routed design. The router makes routing decisions based on computed delay times between sources and loads on the routed nets, and reroutes to minimize the delays. Set the number of delay-based cleanup passes you want to run by choosing a number from 1 to 5. The default is 0.
  
  

Use Timing Constraints During Place and Route

Select this option to produce a high-performance implementation of the design. The router uses the timing constraints in the design file to place and route the design within the specified constraints. Deselect this option to ignore timing constraints. This reduces implementation time at the expense of timing performance. By default, this option is on.

Spartan Timing Reports Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.4 Spartan Timing Reports Tab

Logic Level Timing Report/Post Layout Timing Report

Choose whether you want to generate a logic level timing report, a post layout timing report, or both.

Note: When the Logic Level Timing Report option is enabled, the report is automatically generated as part of the Map step. When the Post Layout Timing Report option is enabled, the report is automatically generated as part of the Place and Route steps.

• Produce Logic Level Timing Report
  
  Select this option to produce a timing report prior to place and route but after map. The timing report provides a summary analysis of your timing constraints based on block delays and estimates of route delays. You can use this report to determine whether you need to revise the timing constraints in your design or create more efficient logic. This feature provides a useful analysis of your timing constraints without the wait required for place and route. To obtain a detailed analysis, use the Timing Analyzer tool after you place and route the design. By default, this option is off.
  
  
• Produce Post Layout Timing Report
  
  Select this option to produce a timing report. The timing report provides a brief analysis of the maximum clock speed for the design after it is placed and routed. To obtain a detailed analysis, use the Timing Analyzer tool. By default, this option is on.
  
  

Both the Logic Level Timing Report and Post Layout Timing Report group boxes contain the following options, which control the number of reported paths for each timing constraint and the format of the report. The default timing report format is Report Paths Failing Timing Constraints.

At the top of each type of report, there is descriptive information such as the software version of the application, the name of the design file, the input physical constraints (PCF) file name, the device speed and the report level. A timing summary always appears at the end of the report. For error and path reports, entries are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). Error and path reports also contain a list of all time groups defined in the PCF file and all of the members defined within each group.

• Limit Report to _ Paths per Timing Constraint
  
  Use this option to set the maximum number of reported paths for each timing constraint. The report displays worst-case paths. Choose Summary, No Limit, or a value from 1 to 10. The Summary report indicates whether your timing constraints are being met and the maximum frequency for your clocks. It also indicates if errors exist.
  
  The default setting is 1 for the Logic Level Timing Report and 3 for the Post Layout Timing Report.
  
  
• Report Paths Using Advanced Design Analysis
  
  Select this option only if you are not supplying any timing constraints in a PCF file. This report contains an analysis that enumerates all clocks and the required OFFSETs for each clock. It also contains an analysis of paths having only combinatorial logic, ordered by delay.
  
  
• Report Paths in Timing Constraints
  
  Select this option to generate a report of the paths and path delays covered by the timing constraints that you specified in your design or UCF file. The number of paths per constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.
  
  
• Report Paths Failing Timing Constraints
  
  Select this option to generate an error report. The error report lists timing errors and associated net/path delay information. Failed paths appear listed from worst-case to best-case.
  
  If a constraint is not met, the report gives the number of items scored, the number of errors encountered, and a detailed breakdown of the error. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical element and the logic element from which the physical element was generated. If a constraint is met, the report states the number of items scored, reports no timing errors detected, and issues a brief report line.
  
  The number of errors listed for each constraint is limited to the number you specify with the Limit Report to _ Paths per Timing Constraint option.