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By default, the Timing Analyzer analyzes and reports on all paths in a design. However, you can determine the appearance and the content of the reports that the Timing Analyzer generates.
Perform the steps described in the following sections to customize generated reports. Each section describes a report output option you can specify.
Option | FPGA | CPLD |
---|---|---|
Summary Only | Yes | No |
No Limit | Yes | Yes |
Limit Report To | Yes | Yes |
Report Delays Less Than | No | Yes |
Report Delays Greater Than | No | Yes |
Sort On | No | Yes |
Report Only Longest Paths Between Points | No | Yes |
Wide Report | Yes | Yes |
Note: The Summary Only option only applies to FPGAs; it is disabled if a CPLD design is open.
To generate a summary report, select Summary Only in the Report Options dialog box. A summary report contains only the path source and end point. It lists one delay path per line and does not display cumulative delays.
To limit the total number of paths per timing constraint that the Timing Analyzer reports, select the Limit Report To radio button and enter a value in the Limit Report To field.
You can use this option with the criterion you specify in the Sort On field when generating an Custom Analysis report. For example, if you enter 10 in the Maximum Number of Paths per Timing Constraint field and set the Sort On option to Descending Delay, the Timing Analyzer reports the 10 paths with the longest delay.
You can optionally use a keyboard command to set this option.
Note: This option only supports analysis of CPLD designs; it is disabled if an FPGA design is open.
To instruct the Timing Analyzer to report only those paths that have a delay less than or equal to the specified value, enter a value, in nanoseconds in the Report Delays Less Than field of the Report Options dialog box. Make the field blank to include paths regardless of how large the delays are.
Note: This option only supports analysis of CPLD designs; it is disabled if an FPGA design is open.
You can instruct the Timing Analyzer to report only those paths that have a delay greater than or equal to the specified value. To do so, enter a value, in nanoseconds, in the Report Delays Greater Than, field of the Report Options dialog box.
Note: This option only supports analysis of CPLD designs; it is disabled if an FPGA design is open.
You can specify how the Timing Analyzer sorts path types when they are reported. To specify how paths are sorted, click on the down arrow next to the Sort On field in the Report Options dialog box, and select a path type. See the Report Options (Options Menu) section of the Menu Commands chapter for descriptions of these delay path types.
Note: This option only supports analysis of CPLD designs; it is disabled if an FPGA design is open.
If there is more than one path between two end points, you can direct the Timing Analyzer to report only the path with the longest delay. Select Report Only Longest Paths Between Points in the Report Options dialog box.
By default, the Timing Analyzer generates a report formatted with 80 characters per line. To generate a wide report, select Wide Report. Wide reports have 132 characters per line. They help reduce the number of truncated net names, since names are truncated to 132 characters instead of 80 characters as in a default report.