Schematic Designs in the HDL Flow

To take advantage of cross-boundary optimization and top-down synthesis methodology, you can use the HDL flow instead of the Schematic flow for top-level schematic designs with underlying HDL macros. In the HDL flow, your entire design is synthesized and optimized resulting in overall design performance improvement. The HDL flow is recommended for schematic top-level designs that contain underlying HDL macros. Used in this way, the tool behaves like an HDL block level diagram editor.

The following sections describe the HDL flow procedure for top-level schematic designs containing underlying HDL macros.

Adding a Schematic Library

In an HDL flow project, the device family is not selected until the design is synthesized. Therefore, you need to add a Xilinx library manually to make the Xilinx components available for schematic entry.

1. From the Project Manager window, select File Project Libraries.
   
   
   
   
2. Select the target library for the desired device in the Attached Libraries window.
   
   
3. Click Add to add the library to your project. The library name will appear in the Files tab.
   
   

   Note: If you want to create a top-level schematic to act only as a block diagram for your HDL designs, you do not need to add a schematic library.

Creating HDL Macros

Use the following procedure to create a macro from an HDL file (or State Machine) for use in a schematic.

1. Click the HDL Editor on the Design Entry button on the Project Manager's Flow tab.
   
   
2. Create or open an HDL file in the HDL Editor.
   
   
3. To create a symbol for the HDL file after you have finished editing or creating the file, select Project Create Macro from the HDL Editor. The symbol is created and added to the SC Symbols list.
   
   (If you are asked for an initial target device when the macro is being created, enter any device. The synthesis that is done here is only necessary to create the symbol.)
   
   

   Note: If the Create Macro or Update Macro option is not available, check whether the HDL file has already been “added” to the project. If it is listed in the Files tab of the Project Manager, it is currently “added” to the project. Remove the file from the project by selecting it and choosing Document Remove. You can now create the macro. The file will be automatically added to the project when the entire design is analyzed later.

Creating the Schematic and Generating a Netlist

This section lists the basic steps for creating a schematic and generating a netlist from it.

1. Open the Schematic Editor by selecting the Schematic Editor icon from the Design Entry box on the Project Manager's Flow tab.
   
   
   
   
2. Select Mode Symbols to add components to your new schematic. Select specific components from the SC Symbols window.
   
   
3. To define the ports, use Hierarchy Connectors.
   
   
   
   Do not use pad components (IPAD, OPAD, etc.) from the Xilinx Unified Libraries. Foundation will synthesize the design from the top down and will add ports as well as buffers, if necessary.
   
   Care must be taken when adding attributes to the schematic as follows:
   
   
4. Pin locations, slew rates, and certain other design constraints may be added to the design using the Express Constraints Editor or a UCF file.
   
   
   • Pin location or slew rate constraints may be placed on the I/O buffer (or flip-flop or latch) on the schematic. Do not place them on the net or the hierarchy connector.
     
     
5. Save your schematic by selecting File Save.
   
   
6. Add the schematic to your project by selecting Hierarchy Add Current Sheet to Project. The schematic is netlisted and added to the project. The schematic (as well as any underlying HDL files) appear in the Files tab.
   
   

   Note: If the HDL macros in the schematic have lower levels of hierarchy or use user-defined libraries, you must add the files for the lower levels to your project manually. Select Document Add from the Project Manager to add the files. Foundation needs access to all the design files before synthesis can occur.

Selecting a Netlist Format

When a schematic is added to the project or when Foundation analyzes the schematic portion of the design, the schematic is netlisted into one of three formats: VHDL, XNF, or EDIF. (By default, VHDL is used.)

From the Project Manager, select Synthesis Options and choose a netlist format in the “Export schematics to” section based on the following criteria.

• If the design is only a block diagram (there are no Unified Library components), use VHDL.
  
  
• If no attributes are passed from the schematic (including within Xilinx macros), use VHDL
  
  
• If the schematic includes XNF macros that contain RLOCs, use VHDL or select the Preserve Hierarchy option (in the Synthesis Settings dialog box).
  
  
• If any attributes have been applied within the schematic, then select XNF or EDIF.
  
  
• If the design targets a Virtex device, XNF may not be used.
  
  

Completing the design

Synthesize the design in the same manner you would a top-level HDL design.

1. Click the Synthesis (or Implementation) button on the Flow tab.
   
   
2. Select the schematic as the top-level in the Synthesis/Implementation settings dialog box.
   
   
3. In the Target Device section, be sure to select the device family that matches the schematic library you added to the project.
   
   
4. Click Run.
   
   

Foundation links all the project files and synthesizes the design using the top-down methodology.

HDL files from the schematic are added to the project when the schematic is analyzed. All HDL and State Machine files for which schematic macros were created are added to the Files tab. You may open and edit these files by double clicking on them in the Files tab. However, you can only update the HDL macros by opening them from the Schematic Editor and then selecting Project Update Macro.

For more information on completing an HDL flow project, refer to the “Synthesizing the Design”through the “Programming the Device” sections under the “All-HDL Designs” section.